-/************* QLogic 25G/40G/100G vendor/devices ids *************/
-#define PCI_VENDOR_ID_QLOGIC 0x1077
-
-#define CHIP_NUM_57980E 0x1634
-#define CHIP_NUM_57980S 0x1629
-#define CHIP_NUM_VF 0x1630
-#define CHIP_NUM_57980S_40 0x1634
-#define CHIP_NUM_57980S_25 0x1656
-#define CHIP_NUM_57980S_IOV 0x1664
-#define CHIP_NUM_57980S_100 0x1644
-
-#define PCI_DEVICE_ID_NX2_57980E CHIP_NUM_57980E
-#define PCI_DEVICE_ID_NX2_57980S CHIP_NUM_57980S
-#define PCI_DEVICE_ID_NX2_VF CHIP_NUM_VF
-#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
-#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
-#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
-#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
-
-extern char fw_file[];
-
-/* Port/function states */
-enum dev_state {
- QEDE_START,
- QEDE_STOP,
- QEDE_CLOSE
+/************* QLogic 10G/25G/40G/50G/100G vendor/devices ids *************/
+#define PCI_VENDOR_ID_QLOGIC 0x1077
+
+#define CHIP_NUM_57980E 0x1634
+#define CHIP_NUM_57980S 0x1629
+#define CHIP_NUM_VF 0x1630
+#define CHIP_NUM_57980S_40 0x1634
+#define CHIP_NUM_57980S_25 0x1656
+#define CHIP_NUM_57980S_IOV 0x1664
+#define CHIP_NUM_57980S_100 0x1644
+#define CHIP_NUM_57980S_50 0x1654
+#define CHIP_NUM_AH_50G 0x8070
+#define CHIP_NUM_AH_10G 0x8071
+#define CHIP_NUM_AH_40G 0x8072
+#define CHIP_NUM_AH_25G 0x8073
+#define CHIP_NUM_AH_IOV 0x8090
+
+#define PCI_DEVICE_ID_QLOGIC_NX2_57980E CHIP_NUM_57980E
+#define PCI_DEVICE_ID_QLOGIC_NX2_57980S CHIP_NUM_57980S
+#define PCI_DEVICE_ID_QLOGIC_NX2_VF CHIP_NUM_VF
+#define PCI_DEVICE_ID_QLOGIC_57980S_40 CHIP_NUM_57980S_40
+#define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25
+#define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV
+#define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100
+#define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50
+#define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G
+#define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G
+#define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G
+#define PCI_DEVICE_ID_QLOGIC_AH_25G CHIP_NUM_AH_25G
+#define PCI_DEVICE_ID_QLOGIC_AH_IOV CHIP_NUM_AH_IOV
+
+
+
+extern char qede_fw_file[];
+
+/* Number of PF connections - 32 RX + 32 TX */
+#define QEDE_PF_NUM_CONNS (64)
+
+/* Maximum number of flowdir filters */
+#define QEDE_RFS_MAX_FLTR (256)
+
+#define QEDE_MAX_MCAST_FILTERS (64)
+
+enum qed_filter_rx_mode_type {
+ QED_FILTER_RX_MODE_TYPE_REGULAR,
+ QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC,
+ QED_FILTER_RX_MODE_TYPE_PROMISC,
+};
+
+struct qede_vlan_entry {
+ SLIST_ENTRY(qede_vlan_entry) list;
+ uint16_t vid;
+};
+
+struct qede_mcast_entry {
+ struct rte_ether_addr mac;
+ SLIST_ENTRY(qede_mcast_entry) list;
+};
+
+struct qede_ucast_entry {
+ struct rte_ether_addr mac;
+ uint16_t vlan;
+ uint16_t vni;
+ SLIST_ENTRY(qede_ucast_entry) list;
+};
+
+#ifndef IPV6_ADDR_LEN
+#define IPV6_ADDR_LEN (16)
+#endif
+
+struct qede_arfs_tuple {
+ union {
+ uint32_t src_ipv4;
+ uint8_t src_ipv6[IPV6_ADDR_LEN];
+ };
+
+ union {
+ uint32_t dst_ipv4;
+ uint8_t dst_ipv6[IPV6_ADDR_LEN];
+ };
+
+ uint16_t src_port;
+ uint16_t dst_port;
+ uint16_t eth_proto;
+ uint8_t ip_proto;
+
+ /* Describe filtering mode needed for this kind of filter */
+ enum ecore_filter_config_mode mode;