#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2_LL TLV_PORT_MODE_2x1_2x1_LL /* Dual 25G on mdi0, dual 25G on mdi1, low-latency PCS */
#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_LL TLV_PORT_MODE_4x1_NA_LL /* Quad 25G on mdi0, low-latency PCS */
#define TLV_PORT_MODE_25G_25G_25G_25G_Q2_LL TLV_PORT_MODE_NA_4x1_LL /* Quad 25G on mdi1, low-latency PCS */
#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2_LL TLV_PORT_MODE_2x1_2x1_LL /* Dual 25G on mdi0, dual 25G on mdi1, low-latency PCS */
#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_LL TLV_PORT_MODE_4x1_NA_LL /* Quad 25G on mdi0, low-latency PCS */
#define TLV_PORT_MODE_25G_25G_25G_25G_Q2_LL TLV_PORT_MODE_NA_4x1_LL /* Quad 25G on mdi1, low-latency PCS */