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net/af_packet: run on kernel without qdisc bypass support
[dpdk.git]
/
drivers
/
net
/
sfc
/
sfc_dp.h
diff --git
a/drivers/net/sfc/sfc_dp.h
b/drivers/net/sfc/sfc_dp.h
index
3da65ab
..
61c1a3f
100644
(file)
--- a/
drivers/net/sfc/sfc_dp.h
+++ b/
drivers/net/sfc/sfc_dp.h
@@
-1,7
+1,7
@@
/* SPDX-License-Identifier: BSD-3-Clause
*
/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright
(c) 2017-2018 Solarflare Communications
Inc.
- *
All rights reserved
.
+ * Copyright
(c) 2019-2021 Xilinx,
Inc.
+ *
Copyright(c) 2017-2019 Solarflare Communications Inc
.
*
* This software was jointly developed between OKTET Labs (under contract
* for Solarflare) and Solarflare Communications, Inc.
*
* This software was jointly developed between OKTET Labs (under contract
* for Solarflare) and Solarflare Communications, Inc.
@@
-51,6
+51,11
@@
void sfc_dp_queue_init(struct sfc_dp_queue *dpq,
uint16_t port_id, uint16_t queue_id,
const struct rte_pci_addr *pci_addr);
uint16_t port_id, uint16_t queue_id,
const struct rte_pci_addr *pci_addr);
+/* Maximum datapath log level to be included in build. */
+#ifndef SFC_DP_LOG_LEVEL
+#define SFC_DP_LOG_LEVEL RTE_LOG_NOTICE
+#endif
+
/*
* Helper macro to define datapath logging macros and have uniform
* logging.
/*
* Helper macro to define datapath logging macros and have uniform
* logging.
@@
-60,6
+65,8
@@
void sfc_dp_queue_init(struct sfc_dp_queue *dpq,
const struct sfc_dp_queue *_dpq = (dpq); \
const struct rte_pci_addr *_addr = &(_dpq)->pci_addr; \
\
const struct sfc_dp_queue *_dpq = (dpq); \
const struct rte_pci_addr *_addr = &(_dpq)->pci_addr; \
\
+ if (RTE_LOG_ ## level > SFC_DP_LOG_LEVEL) \
+ break; \
SFC_GENERIC_LOG(level, \
RTE_FMT("%s " PCI_PRI_FMT \
" #%" PRIu16 ".%" PRIu16 ": " \
SFC_GENERIC_LOG(level, \
RTE_FMT("%s " PCI_PRI_FMT \
" #%" PRIu16 ".%" PRIu16 ": " \
@@
-81,11
+88,20
@@
struct sfc_dp {
unsigned int hw_fw_caps;
#define SFC_DP_HW_FW_CAP_EF10 0x1
#define SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER 0x2
unsigned int hw_fw_caps;
#define SFC_DP_HW_FW_CAP_EF10 0x1
#define SFC_DP_HW_FW_CAP_RX_ES_SUPER_BUFFER 0x2
+#define SFC_DP_HW_FW_CAP_RX_EFX 0x4
+#define SFC_DP_HW_FW_CAP_TX_EFX 0x8
+#define SFC_DP_HW_FW_CAP_EF100 0x10
};
/** List of datapath variants */
TAILQ_HEAD(sfc_dp_list, sfc_dp);
};
/** List of datapath variants */
TAILQ_HEAD(sfc_dp_list, sfc_dp);
+typedef unsigned int sfc_sw_index_t;
+#define SFC_SW_INDEX_INVALID ((sfc_sw_index_t)(UINT_MAX))
+
+typedef int32_t sfc_ethdev_qid_t;
+#define SFC_ETHDEV_QID_INVALID ((sfc_ethdev_qid_t)(-1))
+
/* Check if available HW/FW capabilities are sufficient for the datapath */
static inline bool
sfc_dp_match_hw_fw_caps(const struct sfc_dp *dp, unsigned int avail_caps)
/* Check if available HW/FW capabilities are sufficient for the datapath */
static inline bool
sfc_dp_match_hw_fw_caps(const struct sfc_dp *dp, unsigned int avail_caps)