+int
+sfc_mae_switch_domain_controllers(uint16_t switch_domain_id,
+ const efx_pcie_interface_t **controllers,
+ size_t *nb_controllers)
+{
+ struct sfc_mae_switch_domain *domain;
+
+ if (controllers == NULL || nb_controllers == NULL)
+ return EINVAL;
+
+ rte_spinlock_lock(&sfc_mae_switch.lock);
+
+ domain = sfc_mae_find_switch_domain_by_id(switch_domain_id);
+ if (domain == NULL) {
+ rte_spinlock_unlock(&sfc_mae_switch.lock);
+ return EINVAL;
+ }
+
+ *controllers = domain->controllers;
+ *nb_controllers = domain->nb_controllers;
+
+ rte_spinlock_unlock(&sfc_mae_switch.lock);
+ return 0;
+}
+
+int
+sfc_mae_switch_domain_map_controllers(uint16_t switch_domain_id,
+ efx_pcie_interface_t *controllers,
+ size_t nb_controllers)
+{
+ struct sfc_mae_switch_domain *domain;
+
+ rte_spinlock_lock(&sfc_mae_switch.lock);
+
+ domain = sfc_mae_find_switch_domain_by_id(switch_domain_id);
+ if (domain == NULL) {
+ rte_spinlock_unlock(&sfc_mae_switch.lock);
+ return EINVAL;
+ }
+
+ /* Controller mapping may be set only once */
+ if (domain->controllers != NULL) {
+ rte_spinlock_unlock(&sfc_mae_switch.lock);
+ return EINVAL;
+ }
+
+ domain->controllers = controllers;
+ domain->nb_controllers = nb_controllers;
+
+ rte_spinlock_unlock(&sfc_mae_switch.lock);
+ return 0;
+}
+
+int
+sfc_mae_switch_domain_get_controller(uint16_t switch_domain_id,
+ efx_pcie_interface_t intf,
+ int *controller)
+{
+ const efx_pcie_interface_t *controllers;
+ size_t nb_controllers;
+ size_t i;
+ int rc;
+
+ rc = sfc_mae_switch_domain_controllers(switch_domain_id, &controllers,
+ &nb_controllers);
+ if (rc != 0)
+ return rc;
+
+ if (controllers == NULL)
+ return ENOENT;
+
+ for (i = 0; i < nb_controllers; i++) {
+ if (controllers[i] == intf) {
+ *controller = i;
+ return 0;
+ }
+ }
+
+ return ENOENT;
+}
+