+/**
+ * Maximum possible number of MAC addresses (limited by IBUF status
+ * register value MAC_COUNT which has 5 bits).
+ */
+#define SZEDATA2_IBUF_MAX_MAC_COUNT 32
+
+/**
+ * Structure describes IBUF address space.
+ */
+struct szedata2_ibuf {
+ /** Total Received Frames Counter low part */
+ uint32_t trfcl; /**< 0x00 */
+ /** Correct Frames Counter low part */
+ uint32_t cfcl; /**< 0x04 */
+ /** Discarded Frames Counter low part */
+ uint32_t dfcl; /**< 0x08 */
+ /** Counter of frames discarded due to buffer overflow low part */
+ uint32_t bodfcl; /**< 0x0C */
+ /** Total Received Frames Counter high part */
+ uint32_t trfch; /**< 0x10 */
+ /** Correct Frames Counter high part */
+ uint32_t cfch; /**< 0x14 */
+ /** Discarded Frames Counter high part */
+ uint32_t dfch; /**< 0x18 */
+ /** Counter of frames discarded due to buffer overflow high part */
+ uint32_t bodfch; /**< 0x1C */
+ /** IBUF enable register */
+ uint32_t ibuf_en; /**< 0x20 */
+ /** Error mask register */
+ uint32_t err_mask; /**< 0x24 */
+ /** IBUF status register */
+ uint32_t ibuf_st; /**< 0x28 */
+ /** IBUF command register */
+ uint32_t ibuf_cmd; /**< 0x2C */
+ /** Minimum frame length allowed */
+ uint32_t mfla; /**< 0x30 */
+ /** Frame MTU */
+ uint32_t mtu; /**< 0x34 */
+ /** MAC address check mode */
+ uint32_t mac_chmode; /**< 0x38 */
+ /** Octets Received OK Counter low part */
+ uint32_t orocl; /**< 0x3C */
+ /** Octets Received OK Counter high part */
+ uint32_t oroch; /**< 0x40 */
+ /** reserved */
+ uint8_t reserved[60]; /**< 0x4C */
+ /** IBUF memory for MAC addresses */
+ uint32_t mac_mem[2 * SZEDATA2_IBUF_MAX_MAC_COUNT]; /**< 0x80 */
+} __rte_packed;
+
+/**
+ * Structure describes OBUF address space.
+ */
+struct szedata2_obuf {
+ /** Total Sent Frames Counter low part */
+ uint32_t tsfcl; /**< 0x00 */
+ /** Octets Sent Counter low part */
+ uint32_t oscl; /**< 0x04 */
+ /** Total Discarded Frames Counter low part */
+ uint32_t tdfcl; /**< 0x08 */
+ /** reserved */
+ uint32_t reserved1; /**< 0x0C */
+ /** Total Sent Frames Counter high part */
+ uint32_t tsfch; /**< 0x10 */
+ /** Octets Sent Counter high part */
+ uint32_t osch; /**< 0x14 */
+ /** Total Discarded Frames Counter high part */
+ uint32_t tdfch; /**< 0x18 */
+ /** reserved */
+ uint32_t reserved2; /**< 0x1C */
+ /** OBUF enable register */
+ uint32_t obuf_en; /**< 0x20 */
+ /** reserved */
+ uint64_t reserved3; /**< 0x24 */
+ /** OBUF control register */
+ uint32_t ctrl; /**< 0x2C */
+ /** OBUF status register */
+ uint32_t obuf_st; /**< 0x30 */
+} __rte_packed;
+
+/**
+ * Wrapper for reading 4 bytes from device memory in correct endianness.
+ *
+ * @param addr
+ * Address for reading.
+ * @return
+ * 4 B value.
+ */
+static inline uint32_t
+szedata2_read32(const volatile void *addr)
+{
+ return rte_le_to_cpu_32(rte_read32(addr));
+}
+
+/**
+ * Wrapper for writing 4 bytes to device memory in correct endianness.
+ *
+ * @param value
+ * Value to write.
+ * @param addr
+ * Address for writing.
+ */
+static inline void
+szedata2_write32(uint32_t value, volatile void *addr)
+{
+ rte_write32(rte_cpu_to_le_32(value), addr);
+}
+