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net/mlx4: drop inline receive support
[dpdk.git]
/
drivers
/
net
/
thunderx
/
base
/
nicvf_hw.h
diff --git
a/drivers/net/thunderx/base/nicvf_hw.h
b/drivers/net/thunderx/base/nicvf_hw.h
index
a6cda82
..
b7d0a3d
100644
(file)
--- a/
drivers/net/thunderx/base/nicvf_hw.h
+++ b/
drivers/net/thunderx/base/nicvf_hw.h
@@
-1,7
+1,7
@@
/*
* BSD LICENSE
*
/*
* BSD LICENSE
*
- * Copyright (C) Cavium
networks Ltd
. 2016.
+ * Copyright (C) Cavium
, Inc
. 2016.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@
-13,7
+13,7
@@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
- * * Neither the name of Cavium
networks
nor the names of its
+ * * Neither the name of Cavium
, Inc
nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
@@
-43,6
+43,7
@@
#define PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF 0xA11E
#define PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF 0xA134
#define PCI_SUB_DEVICE_ID_CN81XX_NICVF 0xA234
#define PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF 0xA11E
#define PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF 0xA134
#define PCI_SUB_DEVICE_ID_CN81XX_NICVF 0xA234
+#define PCI_SUB_DEVICE_ID_CN83XX_NICVF 0xA334
#define NICVF_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#define NICVF_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
@@
-54,6
+55,8
@@
#define NICVF_CAP_TUNNEL_PARSING (1ULL << 0)
/* Additional word in Rx descriptor to hold optional tunneling extension info */
#define NICVF_CAP_CQE_RX2 (1ULL << 1)
#define NICVF_CAP_TUNNEL_PARSING (1ULL << 0)
/* Additional word in Rx descriptor to hold optional tunneling extension info */
#define NICVF_CAP_CQE_RX2 (1ULL << 1)
+/* The device capable of setting NIC_CQE_RX_S[APAD] == 0 */
+#define NICVF_CAP_DISABLE_APAD (1ULL << 2)
enum nicvf_tns_mode {
NIC_TNS_BYPASS_MODE,
enum nicvf_tns_mode {
NIC_TNS_BYPASS_MODE,
@@
-85,7
+88,7
@@
enum nicvf_err_e {
NICVF_ERR_RSS_GET_SZ, /* -8171 */
};
NICVF_ERR_RSS_GET_SZ, /* -8171 */
};
-typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *opaque);
+typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *
dev, void *
opaque);
struct nicvf_hw_rx_qstats {
uint64_t q_rx_bytes;
struct nicvf_hw_rx_qstats {
uint64_t q_rx_bytes;
@@
-194,8
+197,8
@@
int nicvf_qset_reclaim(struct nicvf *nic);
int nicvf_qset_rbdr_config(struct nicvf *nic, uint16_t qidx);
int nicvf_qset_rbdr_reclaim(struct nicvf *nic, uint16_t qidx);
int nicvf_qset_rbdr_config(struct nicvf *nic, uint16_t qidx);
int nicvf_qset_rbdr_reclaim(struct nicvf *nic, uint16_t qidx);
-int nicvf_qset_rbdr_precharge(
struct nicvf *nic, uint16_t ridx
,
-
rbdr_pool_get_handler handler, void *opaque
,
+int nicvf_qset_rbdr_precharge(
void *dev, struct nicvf *nic
,
+
uint16_t ridx, rbdr_pool_get_handler handler
,
uint32_t max_buffs);
int nicvf_qset_rbdr_active(struct nicvf *nic, uint16_t qidx);
uint32_t max_buffs);
int nicvf_qset_rbdr_active(struct nicvf *nic, uint16_t qidx);
@@
-217,6
+220,8
@@
uint32_t nicvf_qsize_sq_roundup(uint32_t val);
void nicvf_vlan_hw_strip(struct nicvf *nic, bool enable);
void nicvf_vlan_hw_strip(struct nicvf *nic, bool enable);
+void nicvf_apad_config(struct nicvf *nic, bool enable);
+
int nicvf_rss_config(struct nicvf *nic, uint32_t qcnt, uint64_t cfg);
int nicvf_rss_term(struct nicvf *nic);
int nicvf_rss_config(struct nicvf *nic, uint32_t qcnt, uint64_t cfg);
int nicvf_rss_term(struct nicvf *nic);