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gso: support TCP/IPv4 GSO
[dpdk.git]
/
lib
/
librte_eal
/
common
/
include
/
arch
/
ppc_64
/
rte_atomic.h
diff --git
a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
index
b8bc2c0
..
150810c
100644
(file)
--- a/
lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
+++ b/
lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
@@
-46,6
+46,7
@@
extern "C" {
#endif
extern "C" {
#endif
+#include <stdint.h>
#include "generic/rte_atomic.h"
/**
#include "generic/rte_atomic.h"
/**
@@
-62,7
+63,11
@@
extern "C" {
* Guarantees that the STORE operations generated before the barrier
* occur before the STORE operations generated after.
*/
* Guarantees that the STORE operations generated before the barrier
* occur before the STORE operations generated after.
*/
+#ifdef RTE_ARCH_64
+#define rte_wmb() {asm volatile("lwsync" : : : "memory"); }
+#else
#define rte_wmb() {asm volatile("sync" : : : "memory"); }
#define rte_wmb() {asm volatile("sync" : : : "memory"); }
+#endif
/**
* Read memory barrier.
/**
* Read memory barrier.
@@
-70,13
+75,23
@@
extern "C" {
* Guarantees that the LOAD operations generated before the barrier
* occur before the LOAD operations generated after.
*/
* Guarantees that the LOAD operations generated before the barrier
* occur before the LOAD operations generated after.
*/
+#ifdef RTE_ARCH_64
+#define rte_rmb() {asm volatile("lwsync" : : : "memory"); }
+#else
#define rte_rmb() {asm volatile("sync" : : : "memory"); }
#define rte_rmb() {asm volatile("sync" : : : "memory"); }
+#endif
#define rte_smp_mb() rte_mb()
#define rte_smp_mb() rte_mb()
-#define rte_smp_wmb() rte_compiler_barrier()
+#define rte_smp_wmb() rte_wmb()
+
+#define rte_smp_rmb() rte_rmb()
+
+#define rte_io_mb() rte_mb()
+
+#define rte_io_wmb() rte_wmb()
-#define rte_
smp_rmb() rte_compiler_barrier
()
+#define rte_
io_rmb() rte_rmb
()
/*------------------------- 16 bit atomic operations -------------------------*/
/* To be compatible with Power7, use GCC built-in functions for 16 bit
/*------------------------- 16 bit atomic operations -------------------------*/
/* To be compatible with Power7, use GCC built-in functions for 16 bit
@@
-109,12
+124,12
@@
rte_atomic16_dec(rte_atomic16_t *v)
static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
{
static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
{
- return
(__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0)
;
+ return
__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0
;
}
static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
{
}
static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
{
- return
(__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0)
;
+ return
__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0
;
}
/*------------------------- 32 bit atomic operations -------------------------*/
}
/*------------------------- 32 bit atomic operations -------------------------*/
@@
-198,7
+213,7
@@
static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
: [cnt] "r" (&v->cnt)
: "cc", "xer", "memory");
: [cnt] "r" (&v->cnt)
: "cc", "xer", "memory");
- return
(ret == 0)
;
+ return
ret == 0
;
}
static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
}
static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
@@
-216,7
+231,7
@@
static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
: [cnt] "r" (&v->cnt)
: "cc", "xer", "memory");
: [cnt] "r" (&v->cnt)
: "cc", "xer", "memory");
- return
(ret == 0)
;
+ return
ret == 0
;
}
/*------------------------- 64 bit atomic operations -------------------------*/
}
/*------------------------- 64 bit atomic operations -------------------------*/
@@
-387,7
+402,7
@@
static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
: [cnt] "r" (&v->cnt)
: "cc", "xer", "memory");
: [cnt] "r" (&v->cnt)
: "cc", "xer", "memory");
- return
(ret == 0)
;
+ return
ret == 0
;
}
static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
}
static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
@@
-405,7
+420,7
@@
static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
: [cnt] "r" (&v->cnt)
: "cc", "xer", "memory");
: [cnt] "r" (&v->cnt)
: "cc", "xer", "memory");
- return
(ret == 0)
;
+ return
ret == 0
;
}
static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
}
static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)