* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*/
#define ETH_RSS ETH_MQ_RX_RSS
#define VMDQ_DCB ETH_MQ_RX_VMDQ_DCB
#define ETH_DCB_RX ETH_MQ_RX_DCB
/**
*/
#define ETH_RSS ETH_MQ_RX_RSS
#define VMDQ_DCB ETH_MQ_RX_VMDQ_DCB
#define ETH_DCB_RX ETH_MQ_RX_DCB
/**
- ETH_MQ_TX_NONE = 0, /**< It is in neither DCB nor VT mode. */
- ETH_MQ_TX_DCB, /**< For TX side,only DCB is on. */
+ ETH_MQ_TX_NONE = 0, /**< It is in neither DCB nor VT mode. */
+ ETH_MQ_TX_DCB, /**< For TX side,only DCB is on. */
ETH_MQ_TX_VMDQ_DCB, /**< For TX side,both DCB and VT is on. */
ETH_MQ_TX_VMDQ_ONLY, /**< Only VT on, no DCB */
};
/**
ETH_MQ_TX_VMDQ_DCB, /**< For TX side,both DCB and VT is on. */
ETH_MQ_TX_VMDQ_ONLY, /**< Only VT on, no DCB */
};
/**
#define ETH_RSS_PROTO_MASK 0x01FF /**< Mask of valid RSS hash protocols */
/* Definitions used for redirection table entry size */
#define ETH_RSS_RETA_NUM_ENTRIES 128
#define ETH_RSS_PROTO_MASK 0x01FF /**< Mask of valid RSS hash protocols */
/* Definitions used for redirection table entry size */
#define ETH_RSS_RETA_NUM_ENTRIES 128
/* Definitions used for VMDQ and DCB functionality */
#define ETH_VMDQ_MAX_VLAN_FILTERS 64 /**< Maximum nb. of VMDQ vlan filters. */
/* Definitions used for VMDQ and DCB functionality */
#define ETH_VMDQ_MAX_VLAN_FILTERS 64 /**< Maximum nb. of VMDQ vlan filters. */
/* DCB capability defines */
#define ETH_DCB_PG_SUPPORT 0x00000001 /**< Priority Group(ETS) support. */
/* DCB capability defines */
#define ETH_DCB_PG_SUPPORT 0x00000001 /**< Priority Group(ETS) support. */
/* Definitions used for VLAN Offload functionality */
#define ETH_VLAN_STRIP_OFFLOAD 0x0001 /**< VLAN Strip On/Off */
/* Definitions used for VLAN Offload functionality */
#define ETH_VLAN_STRIP_OFFLOAD 0x0001 /**< VLAN Strip On/Off */
#define ETH_VLAN_STRIP_MASK 0x0001 /**< VLAN Strip setting mask */
#define ETH_VLAN_FILTER_MASK 0x0002 /**< VLAN Filter setting mask*/
#define ETH_VLAN_EXTEND_MASK 0x0004 /**< VLAN Extend setting mask*/
#define ETH_VLAN_STRIP_MASK 0x0001 /**< VLAN Strip setting mask */
#define ETH_VLAN_FILTER_MASK 0x0002 /**< VLAN Filter setting mask*/
#define ETH_VLAN_EXTEND_MASK 0x0004 /**< VLAN Extend setting mask*/
/* Definitions used for receive MAC address */
#define ETH_NUM_RECEIVE_MAC_ADDR 128 /**< Maximum nb. of receive mac addr. */
/* Definitions used for receive MAC address */
#define ETH_NUM_RECEIVE_MAC_ADDR 128 /**< Maximum nb. of receive mac addr. */
uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
/**< Possible DCB queue,4 or 8. */
};
uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
/**< Possible DCB queue,4 or 8. */
};
struct rte_eth_vmdq_dcb_tx_conf {
enum rte_eth_nb_pools nb_queue_pools; /**< With DCB, 16 or 32 pools. */
uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
/**< Possible DCB queue,4 or 8. */
};
struct rte_eth_vmdq_dcb_tx_conf {
enum rte_eth_nb_pools nb_queue_pools; /**< With DCB, 16 or 32 pools. */
uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
/**< Possible DCB queue,4 or 8. */
};
struct rte_eth_dcb_tx_conf {
enum rte_eth_nb_tcs nb_tcs; /**< Possible DCB TCs, 4 or 8 TCs. */
uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
struct rte_eth_dcb_tx_conf {
enum rte_eth_nb_tcs nb_tcs; /**< Possible DCB TCs, 4 or 8 TCs. */
uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
struct rte_eth_vmdq_tx_conf vmdq_tx_conf;
/**< Port vmdq TX configuration. */
} tx_adv_conf; /**< Port TX DCB configuration (union). */
struct rte_eth_vmdq_tx_conf vmdq_tx_conf;
/**< Port vmdq TX configuration. */
} tx_adv_conf; /**< Port TX DCB configuration (union). */
- /** Currently,Priority Flow Control(PFC) are supported,if DCB with PFC
- is needed,and the variable must be set ETH_DCB_PFC_SUPPORT. */
- uint32_t dcb_capability_en;
+ /** Currently,Priority Flow Control(PFC) are supported,if DCB with PFC
+ is needed,and the variable must be set ETH_DCB_PFC_SUPPORT. */
+ uint32_t dcb_capability_en;
struct rte_fdir_conf fdir_conf; /**< FDIR configuration. */
struct rte_intr_conf intr_conf; /**< Interrupt mode configuration. */
};
struct rte_fdir_conf fdir_conf; /**< FDIR configuration. */
struct rte_intr_conf intr_conf; /**< Interrupt mode configuration. */
};
uint16_t max_rx_queues; /**< Maximum number of RX queues. */
uint16_t max_tx_queues; /**< Maximum number of TX queues. */
uint32_t max_mac_addrs; /**< Maximum number of MAC addresses. */
uint16_t max_rx_queues; /**< Maximum number of RX queues. */
uint16_t max_tx_queues; /**< Maximum number of TX queues. */
uint32_t max_mac_addrs; /**< Maximum number of MAC addresses. */
/** Maximum number of hash MAC addresses for MTA and UTA. */
uint16_t max_vfs; /**< Maximum number of VFs. */
uint16_t max_vmdq_pools; /**< Maximum number of VMDq pools. */
/** Maximum number of hash MAC addresses for MTA and UTA. */
uint16_t max_vfs; /**< Maximum number of VFs. */
uint16_t max_vmdq_pools; /**< Maximum number of VMDq pools. */
typedef int (*eth_uc_hash_table_set_t)(struct rte_eth_dev *dev,
struct ether_addr *mac_addr,
typedef int (*eth_uc_hash_table_set_t)(struct rte_eth_dev *dev,
struct ether_addr *mac_addr,
uint64_t vf_mask,
uint8_t vlan_on);
/**< @internal Set VF VLAN pool filter */
typedef int (*eth_mirror_rule_set_t)(struct rte_eth_dev *dev,
struct rte_eth_vmdq_mirror_conf *mirror_conf,
uint64_t vf_mask,
uint8_t vlan_on);
/**< @internal Set VF VLAN pool filter */
typedef int (*eth_mirror_rule_set_t)(struct rte_eth_dev *dev,
struct rte_eth_vmdq_mirror_conf *mirror_conf,
void **tx_queues; /**< Array of pointers to TX queues. */
uint16_t nb_rx_queues; /**< Number of RX queues. */
uint16_t nb_tx_queues; /**< Number of TX queues. */
void **tx_queues; /**< Array of pointers to TX queues. */
uint16_t nb_rx_queues; /**< Number of RX queues. */
uint16_t nb_tx_queues; /**< Number of TX queues. */
struct rte_eth_dev_sriov sriov; /**< SRIOV data */
void *dev_private; /**< PMD-specific private data */
struct rte_eth_dev_sriov sriov; /**< SRIOV data */
void *dev_private; /**< PMD-specific private data */
uint64_t rx_mbuf_alloc_failed; /**< RX ring mbuf allocation failures. */
struct ether_addr* mac_addrs;/**< Device Ethernet Link address. */
uint64_t rx_mbuf_alloc_failed; /**< RX ring mbuf allocation failures. */
struct ether_addr* mac_addrs;/**< Device Ethernet Link address. */
/** bitmap array of associating Ethernet MAC addresses to pools */
struct ether_addr* hash_mac_addrs;
/** Device Ethernet MAC addresses of hash filtering. */
/** bitmap array of associating Ethernet MAC addresses to pools */
struct ether_addr* hash_mac_addrs;
/** Device Ethernet MAC addresses of hash filtering. */
dev = &rte_eth_devices[port_id];
return (*dev->dev_ops->rx_queue_count)(dev, queue_id);
}
dev = &rte_eth_devices[port_id];
return (*dev->dev_ops->rx_queue_count)(dev, queue_id);
}
struct rte_eth_rss_reta *reta_conf);
/**
* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device.
struct rte_eth_rss_reta *reta_conf);
/**
* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device.
* 1 - Set an unicast hash bit for receiving packets with the MAC address.
* 0 - Clear an unicast hash bit.
* @return
* 1 - Set an unicast hash bit for receiving packets with the MAC address.
* 0 - Clear an unicast hash bit.
* @return
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENODEV) if *port_id* invalid.
* - (-EINVAL) if bad parameter.
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENODEV) if *port_id* invalid.
* - (-EINVAL) if bad parameter.
- * Updates all unicast hash bitmaps for receiving packet with any Unicast
- * Ethernet MAC addresses,the packet is routed to all VFs for which the RX
+ * Updates all unicast hash bitmaps for receiving packet with any Unicast
+ * Ethernet MAC addresses,the packet is routed to all VFs for which the RX
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENODEV) if *port_id* invalid.
* - (-EINVAL) if bad parameter.
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENODEV) if *port_id* invalid.
* - (-EINVAL) if bad parameter.
* packets that match the PFUTA table, Broadcast and Multicast Promiscuous.
* ETH_VMDQ_ACCEPT_UNTAG,ETH_VMDQ_ACCEPT_HASH_UC,
* ETH_VMDQ_ACCEPT_BROADCAST and ETH_VMDQ_ACCEPT_MULTICAST will be used
* packets that match the PFUTA table, Broadcast and Multicast Promiscuous.
* ETH_VMDQ_ACCEPT_UNTAG,ETH_VMDQ_ACCEPT_HASH_UC,
* ETH_VMDQ_ACCEPT_BROADCAST and ETH_VMDQ_ACCEPT_MULTICAST will be used
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENOTSUP) if hardware doesn't support.
* - (-EINVAL) if bad parameter.
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENOTSUP) if hardware doesn't support.
* - (-EINVAL) if bad parameter.
* - (-ENODEV) if *port_id* invalid.
* - (-ENOTSUP) if hardware doesn't support.
* - (-EINVAL) if bad parameter.
*/
* - (-ENODEV) if *port_id* invalid.
* - (-ENOTSUP) if hardware doesn't support.
* - (-EINVAL) if bad parameter.
*/
rte_eth_dev_set_vf_tx(uint8_t port,uint16_t vf, uint8_t on);
/**
* Enable or disable a VF traffic receive of an Ethernet device.
rte_eth_dev_set_vf_tx(uint8_t port,uint16_t vf, uint8_t on);
/**
* Enable or disable a VF traffic receive of an Ethernet device.
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENODEV) if *port_id* invalid.
* - (-EINVAL) if bad parameter.
*/
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENODEV) if *port_id* invalid.
* - (-EINVAL) if bad parameter.
*/
rte_eth_dev_set_vf_rx(uint8_t port,uint16_t vf, uint8_t on);
/**
* Enable/Disable hardware VF VLAN filtering by an Ethernet device of
* received VLAN packets tagged with a given VLAN Tag Identifier.
rte_eth_dev_set_vf_rx(uint8_t port,uint16_t vf, uint8_t on);
/**
* Enable/Disable hardware VF VLAN filtering by an Ethernet device of
* received VLAN packets tagged with a given VLAN Tag Identifier.
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENODEV) if *port_id* invalid.
* - (-EINVAL) if bad parameter.
*/
int
* - (-ENOTSUP) if hardware doesn't support.
* - (-ENODEV) if *port_id* invalid.
* - (-EINVAL) if bad parameter.
*/
int
* - (-EINVAL) if the mr_conf information is not correct.
*/
int rte_eth_mirror_rule_set(uint8_t port_id,
* - (-EINVAL) if the mr_conf information is not correct.
*/
int rte_eth_mirror_rule_set(uint8_t port_id,