+/* AVX512/VPCLMULQDQ handling */
+
+#define AVX512_VPCLMULQDQ_CPU_SUPPORTED ( \
+ rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) && \
+ rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) && \
+ rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512DQ) && \
+ rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) && \
+ rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ) && \
+ rte_cpu_get_flag_enabled(RTE_CPUFLAG_VPCLMULQDQ) \
+)
+
+static const rte_net_crc_handler *
+avx512_vpclmulqdq_get_handlers(void)
+{
+#ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
+ if (AVX512_VPCLMULQDQ_CPU_SUPPORTED &&
+ max_simd_bitwidth >= RTE_VECT_SIMD_512)
+ return handlers_avx512;
+#endif
+ NET_LOG(INFO, "Requirements not met, can't use AVX512\n");
+ return NULL;
+}
+
+static void
+avx512_vpclmulqdq_init(void)
+{
+#ifdef CC_X86_64_AVX512_VPCLMULQDQ_SUPPORT
+ if (AVX512_VPCLMULQDQ_CPU_SUPPORTED)
+ rte_net_crc_avx512_init();
+#endif
+}
+
+/* SSE4.2/PCLMULQDQ handling */
+
+#define SSE42_PCLMULQDQ_CPU_SUPPORTED \
+ rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ)
+
+static const rte_net_crc_handler *
+sse42_pclmulqdq_get_handlers(void)
+{
+#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
+ if (SSE42_PCLMULQDQ_CPU_SUPPORTED &&
+ max_simd_bitwidth >= RTE_VECT_SIMD_128)
+ return handlers_sse42;
+#endif
+ NET_LOG(INFO, "Requirements not met, can't use SSE\n");
+ return NULL;
+}
+
+static void
+sse42_pclmulqdq_init(void)
+{
+#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT
+ if (SSE42_PCLMULQDQ_CPU_SUPPORTED)
+ rte_net_crc_sse42_init();
+#endif
+}
+
+/* NEON/PMULL handling */
+
+#define NEON_PMULL_CPU_SUPPORTED \
+ rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)
+
+static const rte_net_crc_handler *
+neon_pmull_get_handlers(void)
+{
+#ifdef CC_ARM64_NEON_PMULL_SUPPORT
+ if (NEON_PMULL_CPU_SUPPORTED &&
+ max_simd_bitwidth >= RTE_VECT_SIMD_128)
+ return handlers_neon;
+#endif
+ NET_LOG(INFO, "Requirements not met, can't use NEON\n");
+ return NULL;
+}
+
+static void
+neon_pmull_init(void)
+{
+#ifdef CC_ARM64_NEON_PMULL_SUPPORT
+ if (NEON_PMULL_CPU_SUPPORTED)
+ rte_net_crc_neon_init();
+#endif
+}
+
+/* Default handling */
+
+static uint32_t
+rte_crc16_ccitt_default_handler(const uint8_t *data, uint32_t data_len)
+{
+ handlers = NULL;
+ if (max_simd_bitwidth == 0)
+ max_simd_bitwidth = rte_vect_get_max_simd_bitwidth();
+
+ handlers = avx512_vpclmulqdq_get_handlers();
+ if (handlers != NULL)
+ return handlers[RTE_NET_CRC16_CCITT](data, data_len);
+ handlers = sse42_pclmulqdq_get_handlers();
+ if (handlers != NULL)
+ return handlers[RTE_NET_CRC16_CCITT](data, data_len);
+ handlers = neon_pmull_get_handlers();
+ if (handlers != NULL)
+ return handlers[RTE_NET_CRC16_CCITT](data, data_len);
+ handlers = handlers_scalar;
+ return handlers[RTE_NET_CRC16_CCITT](data, data_len);
+}
+
+static uint32_t
+rte_crc32_eth_default_handler(const uint8_t *data, uint32_t data_len)
+{
+ handlers = NULL;
+ if (max_simd_bitwidth == 0)
+ max_simd_bitwidth = rte_vect_get_max_simd_bitwidth();
+
+ handlers = avx512_vpclmulqdq_get_handlers();
+ if (handlers != NULL)
+ return handlers[RTE_NET_CRC32_ETH](data, data_len);
+ handlers = sse42_pclmulqdq_get_handlers();
+ if (handlers != NULL)
+ return handlers[RTE_NET_CRC32_ETH](data, data_len);
+ handlers = neon_pmull_get_handlers();
+ if (handlers != NULL)
+ return handlers[RTE_NET_CRC32_ETH](data, data_len);
+ handlers = handlers_scalar;
+ return handlers[RTE_NET_CRC32_ETH](data, data_len);
+}
+
+/* Public API */
+