/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2010-2014 Intel Corporation
+ * Copyright(c) 2020 Arm Limited
*/
+#include "test.h"
+
+#ifdef RTE_EXEC_ENV_WINDOWS
+static int
+test_lpm_perf(void)
+{
+ printf("lpm_perf not supported on Windows, skipping test\n");
+ return TEST_SKIPPED;
+}
+
+#else
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <rte_cycles.h>
#include <rte_random.h>
#include <rte_branch_prediction.h>
+#include <rte_malloc.h>
#include <rte_ip.h>
#include <rte_lpm.h>
-#include "test.h"
#include "test_xmmt_ops.h"
+struct rte_lpm *lpm;
+static struct rte_rcu_qsbr *rv;
+static volatile uint8_t writer_done;
+static volatile uint32_t thr_id;
+static uint64_t gwrite_cycles;
+static uint32_t num_writers;
+/* LPM APIs are not thread safe, use mutex to provide thread safety */
+static pthread_mutex_t lpm_mutex = PTHREAD_MUTEX_INITIALIZER;
+
+/* Report quiescent state interval every 1024 lookups. Larger critical
+ * sections in reader will result in writer polling multiple times.
+ */
+#define QSBR_REPORTING_INTERVAL 1024
+
#define TEST_LPM_ASSERT(cond) do { \
if (!(cond)) { \
printf("Error at line %d: \n", __LINE__); \
} while(0)
#define ITERATIONS (1 << 10)
+#define RCU_ITERATIONS 10
#define BATCH_SIZE (1 << 12)
#define BULK_SIZE 32
uint8_t depth;
};
-struct route_rule large_route_table[MAX_RULE_NUM];
+static struct route_rule large_route_table[MAX_RULE_NUM];
+/* Route table for routes with depth > 24 */
+struct route_rule large_ldepth_route_table[MAX_RULE_NUM];
static uint32_t num_route_entries;
+static uint32_t num_ldepth_route_entries;
#define NUM_ROUTE_ENTRIES num_route_entries
+#define NUM_LDEPTH_ROUTE_ENTRIES num_ldepth_route_entries
+
+#define TOTAL_WRITES (RCU_ITERATIONS * NUM_LDEPTH_ROUTE_ENTRIES)
enum {
IP_CLASS_A,
uint32_t ip_head_mask;
uint32_t rule_num;
uint32_t k;
- struct route_rule *ptr_rule;
+ struct route_rule *ptr_rule, *ptr_ldepth_rule;
if (ip_class == IP_CLASS_A) { /* IP Address class A */
fixed_bit_num = IP_HEAD_BIT_NUM_A;
*/
start = lrand48() & mask;
ptr_rule = &large_route_table[num_route_entries];
+ ptr_ldepth_rule = &large_ldepth_route_table[num_ldepth_route_entries];
for (k = 0; k < rule_num; k++) {
ptr_rule->ip = (start << (RTE_LPM_MAX_DEPTH - depth))
| ip_head_mask;
ptr_rule->depth = depth;
+ /* If the depth of the route is more than 24, store it
+ * in another table as well.
+ */
+ if (depth > 24) {
+ ptr_ldepth_rule->ip = ptr_rule->ip;
+ ptr_ldepth_rule->depth = ptr_rule->depth;
+ ptr_ldepth_rule++;
+ num_ldepth_route_entries++;
+ }
ptr_rule++;
start = (start + step) & mask;
}
uint8_t depth;
num_route_entries = 0;
+ num_ldepth_route_entries = 0;
memset(large_route_table, 0, sizeof(large_route_table));
for (ip_class = IP_CLASS_A; ip_class <= IP_CLASS_C; ip_class++) {
printf("\n");
}
+/* Check condition and return an error if true. */
+static uint16_t enabled_core_ids[RTE_MAX_LCORE];
+static unsigned int num_cores;
+
+/* Simple way to allocate thread ids in 0 to RTE_MAX_LCORE space */
+static inline uint32_t
+alloc_thread_id(void)
+{
+ uint32_t tmp_thr_id;
+
+ tmp_thr_id = __atomic_fetch_add(&thr_id, 1, __ATOMIC_RELAXED);
+ if (tmp_thr_id >= RTE_MAX_LCORE)
+ printf("Invalid thread id %u\n", tmp_thr_id);
+
+ return tmp_thr_id;
+}
+
+/*
+ * Reader thread using rte_lpm data structure without RCU.
+ */
+static int
+test_lpm_reader(void *arg)
+{
+ int i;
+ uint32_t ip_batch[QSBR_REPORTING_INTERVAL];
+ uint32_t next_hop_return = 0;
+
+ RTE_SET_USED(arg);
+ do {
+ for (i = 0; i < QSBR_REPORTING_INTERVAL; i++)
+ ip_batch[i] = rte_rand();
+
+ for (i = 0; i < QSBR_REPORTING_INTERVAL; i++)
+ rte_lpm_lookup(lpm, ip_batch[i], &next_hop_return);
+
+ } while (!writer_done);
+
+ return 0;
+}
+
+/*
+ * Reader thread using rte_lpm data structure with RCU.
+ */
+static int
+test_lpm_rcu_qsbr_reader(void *arg)
+{
+ int i;
+ uint32_t thread_id = alloc_thread_id();
+ uint32_t ip_batch[QSBR_REPORTING_INTERVAL];
+ uint32_t next_hop_return = 0;
+
+ RTE_SET_USED(arg);
+ /* Register this thread to report quiescent state */
+ rte_rcu_qsbr_thread_register(rv, thread_id);
+ rte_rcu_qsbr_thread_online(rv, thread_id);
+
+ do {
+ for (i = 0; i < QSBR_REPORTING_INTERVAL; i++)
+ ip_batch[i] = rte_rand();
+
+ for (i = 0; i < QSBR_REPORTING_INTERVAL; i++)
+ rte_lpm_lookup(lpm, ip_batch[i], &next_hop_return);
+
+ /* Update quiescent state */
+ rte_rcu_qsbr_quiescent(rv, thread_id);
+ } while (!writer_done);
+
+ rte_rcu_qsbr_thread_offline(rv, thread_id);
+ rte_rcu_qsbr_thread_unregister(rv, thread_id);
+
+ return 0;
+}
+
+/*
+ * Writer thread using rte_lpm data structure with RCU.
+ */
+static int
+test_lpm_rcu_qsbr_writer(void *arg)
+{
+ unsigned int i, j, si, ei;
+ uint64_t begin, total_cycles;
+ uint32_t next_hop_add = 0xAA;
+ uint8_t pos_core = (uint8_t)((uintptr_t)arg);
+
+ si = (pos_core * NUM_LDEPTH_ROUTE_ENTRIES) / num_writers;
+ ei = ((pos_core + 1) * NUM_LDEPTH_ROUTE_ENTRIES) / num_writers;
+
+ /* Measure add/delete. */
+ begin = rte_rdtsc_precise();
+ for (i = 0; i < RCU_ITERATIONS; i++) {
+ /* Add all the entries */
+ for (j = si; j < ei; j++) {
+ if (num_writers > 1)
+ pthread_mutex_lock(&lpm_mutex);
+ if (rte_lpm_add(lpm, large_ldepth_route_table[j].ip,
+ large_ldepth_route_table[j].depth,
+ next_hop_add) != 0) {
+ printf("Failed to add iteration %d, route# %d\n",
+ i, j);
+ goto error;
+ }
+ if (num_writers > 1)
+ pthread_mutex_unlock(&lpm_mutex);
+ }
+
+ /* Delete all the entries */
+ for (j = si; j < ei; j++) {
+ if (num_writers > 1)
+ pthread_mutex_lock(&lpm_mutex);
+ if (rte_lpm_delete(lpm, large_ldepth_route_table[j].ip,
+ large_ldepth_route_table[j].depth) != 0) {
+ printf("Failed to delete iteration %d, route# %d\n",
+ i, j);
+ goto error;
+ }
+ if (num_writers > 1)
+ pthread_mutex_unlock(&lpm_mutex);
+ }
+ }
+
+ total_cycles = rte_rdtsc_precise() - begin;
+
+ __atomic_fetch_add(&gwrite_cycles, total_cycles, __ATOMIC_RELAXED);
+
+ return 0;
+
+error:
+ if (num_writers > 1)
+ pthread_mutex_unlock(&lpm_mutex);
+ return -1;
+}
+
+/*
+ * Functional test:
+ * 1/2 writers, rest are readers
+ */
+static int
+test_lpm_rcu_perf_multi_writer(uint8_t use_rcu)
+{
+ struct rte_lpm_config config;
+ size_t sz;
+ unsigned int i, j;
+ uint16_t core_id;
+ struct rte_lpm_rcu_config rcu_cfg = {0};
+ int (*reader_f)(void *arg) = NULL;
+
+ if (rte_lcore_count() < 3) {
+ printf("Not enough cores for lpm_rcu_perf_autotest, expecting at least 3\n");
+ return TEST_SKIPPED;
+ }
+
+ num_cores = 0;
+ RTE_LCORE_FOREACH_WORKER(core_id) {
+ enabled_core_ids[num_cores] = core_id;
+ num_cores++;
+ }
+
+ for (j = 1; j < 3; j++) {
+ if (use_rcu)
+ printf("\nPerf test: %d writer(s), %d reader(s),"
+ " RCU integration enabled\n", j, num_cores - j);
+ else
+ printf("\nPerf test: %d writer(s), %d reader(s),"
+ " RCU integration disabled\n", j, num_cores - j);
+
+ num_writers = j;
+
+ /* Create LPM table */
+ config.max_rules = NUM_LDEPTH_ROUTE_ENTRIES;
+ config.number_tbl8s = NUM_LDEPTH_ROUTE_ENTRIES;
+ config.flags = 0;
+ lpm = rte_lpm_create(__func__, SOCKET_ID_ANY, &config);
+ TEST_LPM_ASSERT(lpm != NULL);
+
+ /* Init RCU variable */
+ if (use_rcu) {
+ sz = rte_rcu_qsbr_get_memsize(num_cores);
+ rv = (struct rte_rcu_qsbr *)rte_zmalloc("rcu0", sz,
+ RTE_CACHE_LINE_SIZE);
+ rte_rcu_qsbr_init(rv, num_cores);
+
+ rcu_cfg.v = rv;
+ /* Assign the RCU variable to LPM */
+ if (rte_lpm_rcu_qsbr_add(lpm, &rcu_cfg) != 0) {
+ printf("RCU variable assignment failed\n");
+ goto error;
+ }
+
+ reader_f = test_lpm_rcu_qsbr_reader;
+ } else
+ reader_f = test_lpm_reader;
+
+ writer_done = 0;
+ __atomic_store_n(&gwrite_cycles, 0, __ATOMIC_RELAXED);
+
+ __atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);
+
+ /* Launch reader threads */
+ for (i = j; i < num_cores; i++)
+ rte_eal_remote_launch(reader_f, NULL,
+ enabled_core_ids[i]);
+
+ /* Launch writer threads */
+ for (i = 0; i < j; i++)
+ rte_eal_remote_launch(test_lpm_rcu_qsbr_writer,
+ (void *)(uintptr_t)i,
+ enabled_core_ids[i]);
+
+ /* Wait for writer threads */
+ for (i = 0; i < j; i++)
+ if (rte_eal_wait_lcore(enabled_core_ids[i]) < 0)
+ goto error;
+
+ printf("Total LPM Adds: %d\n", TOTAL_WRITES);
+ printf("Total LPM Deletes: %d\n", TOTAL_WRITES);
+ printf("Average LPM Add/Del: %"PRIu64" cycles\n",
+ __atomic_load_n(&gwrite_cycles, __ATOMIC_RELAXED)
+ / TOTAL_WRITES);
+
+ writer_done = 1;
+ /* Wait until all readers have exited */
+ for (i = j; i < num_cores; i++)
+ rte_eal_wait_lcore(enabled_core_ids[i]);
+
+ rte_lpm_free(lpm);
+ rte_free(rv);
+ lpm = NULL;
+ rv = NULL;
+ }
+
+ return 0;
+
+error:
+ writer_done = 1;
+ /* Wait until all readers have exited */
+ rte_eal_mp_wait_lcore();
+
+ rte_lpm_free(lpm);
+ rte_free(rv);
+
+ return -1;
+}
+
static int
test_lpm_perf(void)
{
- struct rte_lpm *lpm = NULL;
struct rte_lpm_config config;
config.max_rules = 2000000;
lpm = rte_lpm_create(__func__, SOCKET_ID_ANY, &config);
TEST_LPM_ASSERT(lpm != NULL);
- /* Measue add. */
+ /* Measure add. */
begin = rte_rdtsc();
for (i = 0; i < NUM_ROUTE_ENTRIES; i++) {
rte_lpm_delete_all(lpm);
rte_lpm_free(lpm);
+ if (test_lpm_rcu_perf_multi_writer(0) < 0)
+ return -1;
+
+ if (test_lpm_rcu_perf_multi_writer(1) < 0)
+ return -1;
+
return 0;
}
+#endif /* !RTE_EXEC_ENV_WINDOWS */
+
REGISTER_TEST_COMMAND(lpm_perf_autotest, test_lpm_perf);