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cryptodev: use single mempool for asymmetric session
[dpdk.git] / app / test / test_rcu_qsbr_perf.c
diff --git a/app/test/test_rcu_qsbr_perf.c b/app/test/test_rcu_qsbr_perf.c
index 363365f..b15e5ce 100644 (file)
--- a/app/test/test_rcu_qsbr_perf.c
+++ b/app/test/test_rcu_qsbr_perf.c
@@ -17,7 +17,7 @@
 
 /* Check condition and return an error if true. */
 static uint16_t enabled_core_ids[RTE_MAX_LCORE];
-static uint8_t num_cores;
+static unsigned int num_cores;
 
 static uint32_t *keys;
 #define TOTAL_ENTRY (1024 * 8)
@@ -30,8 +30,8 @@ static volatile uint32_t thr_id;
 static struct rte_rcu_qsbr *t[RTE_MAX_LCORE];
 static struct rte_hash *h;
 static char hash_name[8];
-static rte_atomic64_t updates, checks;
-static rte_atomic64_t update_cycles, check_cycles;
+static uint64_t updates, checks;
+static uint64_t update_cycles, check_cycles;
 
 /* Scale down results to 1000 operations to support lower
  * granularity clocks.
@@ -81,8 +81,8 @@ test_rcu_qsbr_reader_perf(void *arg)
        }
 
        cycles = rte_rdtsc_precise() - begin;
-       rte_atomic64_add(&update_cycles, cycles);
-       rte_atomic64_add(&updates, loop_cnt);
+       __atomic_fetch_add(&update_cycles, cycles, __ATOMIC_RELAXED);
+       __atomic_fetch_add(&updates, loop_cnt, __ATOMIC_RELAXED);
 
        /* Make the thread offline */
        rte_rcu_qsbr_thread_offline(t[0], thread_id);
@@ -113,8 +113,8 @@ test_rcu_qsbr_writer_perf(void *arg)
        } while (loop_cnt < 20000000);
 
        cycles = rte_rdtsc_precise() - begin;
-       rte_atomic64_add(&check_cycles, cycles);
-       rte_atomic64_add(&checks, loop_cnt);
+       __atomic_fetch_add(&check_cycles, cycles, __ATOMIC_RELAXED);
+       __atomic_fetch_add(&checks, loop_cnt, __ATOMIC_RELAXED);
        return 0;
 }
 
@@ -125,15 +125,15 @@ test_rcu_qsbr_writer_perf(void *arg)
 static int
 test_rcu_qsbr_perf(void)
 {
-       int i, sz;
-       int tmp_num_cores;
+       size_t sz;
+       unsigned int i, tmp_num_cores;
 
        writer_done = 0;
 
-       rte_atomic64_clear(&updates);
-       rte_atomic64_clear(&update_cycles);
-       rte_atomic64_clear(&checks);
-       rte_atomic64_clear(&check_cycles);
+       __atomic_store_n(&updates, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&checks, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);
 
        printf("\nPerf Test: %d Readers/1 Writer('wait' in qsbr_check == true)\n",
                num_cores - 1);
@@ -167,14 +167,16 @@ test_rcu_qsbr_perf(void)
        /* Wait until all readers have exited */
        rte_eal_mp_wait_lcore();
 
-       printf("Total RCU updates = %"PRIi64"\n", rte_atomic64_read(&updates));
-       printf("Cycles per %d updates: %"PRIi64"\n", RCU_SCALE_DOWN,
-               rte_atomic64_read(&update_cycles) /
-               (rte_atomic64_read(&updates) / RCU_SCALE_DOWN));
-       printf("Total RCU checks = %"PRIi64"\n", rte_atomic64_read(&checks));
+       printf("Total quiescent state updates = %"PRIi64"\n",
+               __atomic_load_n(&updates, __ATOMIC_RELAXED));
+       printf("Cycles per %d quiescent state updates: %"PRIi64"\n",
+               RCU_SCALE_DOWN,
+               __atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /
+               (__atomic_load_n(&updates, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));
+       printf("Total RCU checks = %"PRIi64"\n", __atomic_load_n(&checks, __ATOMIC_RELAXED));
        printf("Cycles per %d checks: %"PRIi64"\n", RCU_SCALE_DOWN,
-               rte_atomic64_read(&check_cycles) /
-               (rte_atomic64_read(&checks) / RCU_SCALE_DOWN));
+               __atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /
+               (__atomic_load_n(&checks, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));
 
        rte_free(t[0]);
 
@@ -188,11 +190,11 @@ test_rcu_qsbr_perf(void)
 static int
 test_rcu_qsbr_rperf(void)
 {
-       int i, sz;
-       int tmp_num_cores;
+       size_t sz;
+       unsigned int i, tmp_num_cores;
 
-       rte_atomic64_clear(&updates);
-       rte_atomic64_clear(&update_cycles);
+       __atomic_store_n(&updates, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);
 
        __atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);
 
@@ -217,10 +219,12 @@ test_rcu_qsbr_rperf(void)
        /* Wait until all readers have exited */
        rte_eal_mp_wait_lcore();
 
-       printf("Total RCU updates = %"PRIi64"\n", rte_atomic64_read(&updates));
-       printf("Cycles per %d updates: %"PRIi64"\n", RCU_SCALE_DOWN,
-               rte_atomic64_read(&update_cycles) /
-               (rte_atomic64_read(&updates) / RCU_SCALE_DOWN));
+       printf("Total quiescent state updates = %"PRIi64"\n",
+               __atomic_load_n(&updates, __ATOMIC_RELAXED));
+       printf("Cycles per %d quiescent state updates: %"PRIi64"\n",
+               RCU_SCALE_DOWN,
+               __atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /
+               (__atomic_load_n(&updates, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));
 
        rte_free(t[0]);
 
@@ -234,10 +238,11 @@ test_rcu_qsbr_rperf(void)
 static int
 test_rcu_qsbr_wperf(void)
 {
-       int i, sz;
+       size_t sz;
+       unsigned int i;
 
-       rte_atomic64_clear(&checks);
-       rte_atomic64_clear(&check_cycles);
+       __atomic_store_n(&checks, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);
 
        __atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);
 
@@ -261,10 +266,10 @@ test_rcu_qsbr_wperf(void)
        /* Wait until all readers have exited */
        rte_eal_mp_wait_lcore();
 
-       printf("Total RCU checks = %"PRIi64"\n", rte_atomic64_read(&checks));
+       printf("Total RCU checks = %"PRIi64"\n", __atomic_load_n(&checks, __ATOMIC_RELAXED));
        printf("Cycles per %d checks: %"PRIi64"\n", RCU_SCALE_DOWN,
-               rte_atomic64_read(&check_cycles) /
-               (rte_atomic64_read(&checks) / RCU_SCALE_DOWN));
+               __atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /
+               (__atomic_load_n(&checks, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));
 
        rte_free(t[0]);
 
@@ -312,8 +317,8 @@ test_rcu_qsbr_hash_reader(void *arg)
        } while (!writer_done);
 
        cycles = rte_rdtsc_precise() - begin;
-       rte_atomic64_add(&update_cycles, cycles);
-       rte_atomic64_add(&updates, loop_cnt);
+       __atomic_fetch_add(&update_cycles, cycles, __ATOMIC_RELAXED);
+       __atomic_fetch_add(&updates, loop_cnt, __ATOMIC_RELAXED);
 
        rte_rcu_qsbr_thread_unregister(temp, thread_id);
 
@@ -378,15 +383,16 @@ static int
 test_rcu_qsbr_sw_sv_1qs(void)
 {
        uint64_t token, begin, cycles;
-       int i, j, tmp_num_cores, sz;
+       size_t sz;
+       unsigned int i, j, tmp_num_cores;
        int32_t pos;
 
        writer_done = 0;
 
-       rte_atomic64_clear(&updates);
-       rte_atomic64_clear(&update_cycles);
-       rte_atomic64_clear(&checks);
-       rte_atomic64_clear(&check_cycles);
+       __atomic_store_n(&updates, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&checks, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);
 
        __atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);
 
@@ -447,8 +453,8 @@ test_rcu_qsbr_sw_sv_1qs(void)
        }
 
        cycles = rte_rdtsc_precise() - begin;
-       rte_atomic64_add(&check_cycles, cycles);
-       rte_atomic64_add(&checks, i);
+       __atomic_fetch_add(&check_cycles, cycles, __ATOMIC_RELAXED);
+       __atomic_fetch_add(&checks, i, __ATOMIC_RELAXED);
 
        writer_done = 1;
 
@@ -460,13 +466,13 @@ test_rcu_qsbr_sw_sv_1qs(void)
        rte_free(keys);
 
        printf("Following numbers include calls to rte_hash functions\n");
-       printf("Cycles per 1 update(online/update/offline): %"PRIi64"\n",
-               rte_atomic64_read(&update_cycles) /
-               rte_atomic64_read(&updates));
+       printf("Cycles per 1 quiescent state update(online/update/offline): %"PRIi64"\n",
+               __atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /
+               __atomic_load_n(&updates, __ATOMIC_RELAXED));
 
        printf("Cycles per 1 check(start, check): %"PRIi64"\n\n",
-               rte_atomic64_read(&check_cycles) /
-               rte_atomic64_read(&checks));
+               __atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /
+               __atomic_load_n(&checks, __ATOMIC_RELAXED));
 
        rte_free(t[0]);
 
@@ -496,14 +502,16 @@ static int
 test_rcu_qsbr_sw_sv_1qs_non_blocking(void)
 {
        uint64_t token, begin, cycles;
-       int i, j, ret, tmp_num_cores, sz;
+       int ret;
+       size_t sz;
+       unsigned int i, j, tmp_num_cores;
        int32_t pos;
 
        writer_done = 0;
 
        printf("Perf test: 1 writer, %d readers, 1 QSBR variable, 1 QSBR Query, Non-Blocking QSBR check\n", num_cores);
 
-       __atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);
+       __atomic_store_n(&thr_id, 0, __ATOMIC_RELAXED);
 
        if (all_registered == 1)
                tmp_num_cores = num_cores;
@@ -562,8 +570,8 @@ test_rcu_qsbr_sw_sv_1qs_non_blocking(void)
        }
 
        cycles = rte_rdtsc_precise() - begin;
-       rte_atomic64_add(&check_cycles, cycles);
-       rte_atomic64_add(&checks, i);
+       __atomic_fetch_add(&check_cycles, cycles, __ATOMIC_RELAXED);
+       __atomic_fetch_add(&checks, i, __ATOMIC_RELAXED);
 
        writer_done = 1;
        /* Wait and check return value from reader threads */
@@ -574,13 +582,13 @@ test_rcu_qsbr_sw_sv_1qs_non_blocking(void)
        rte_free(keys);
 
        printf("Following numbers include calls to rte_hash functions\n");
-       printf("Cycles per 1 update(online/update/offline): %"PRIi64"\n",
-               rte_atomic64_read(&update_cycles) /
-               rte_atomic64_read(&updates));
+       printf("Cycles per 1 quiescent state update(online/update/offline): %"PRIi64"\n",
+               __atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /
+               __atomic_load_n(&updates, __ATOMIC_RELAXED));
 
        printf("Cycles per 1 check(start, check): %"PRIi64"\n\n",
-               rte_atomic64_read(&check_cycles) /
-               rte_atomic64_read(&checks));
+               __atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /
+               __atomic_load_n(&checks, __ATOMIC_RELAXED));
 
        rte_free(t[0]);
 
@@ -606,18 +614,21 @@ test_rcu_qsbr_main(void)
 {
        uint16_t core_id;
 
+       if (RTE_EXEC_ENV_IS_WINDOWS)
+               return TEST_SKIPPED;
+
        if (rte_lcore_count() < 3) {
                printf("Not enough cores for rcu_qsbr_perf_autotest, expecting at least 3\n");
                return TEST_SKIPPED;
        }
 
-       rte_atomic64_init(&updates);
-       rte_atomic64_init(&update_cycles);
-       rte_atomic64_init(&checks);
-       rte_atomic64_init(&check_cycles);
+       __atomic_store_n(&updates, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&checks, 0, __ATOMIC_RELAXED);
+       __atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);
 
        num_cores = 0;
-       RTE_LCORE_FOREACH_SLAVE(core_id) {
+       RTE_LCORE_FOREACH_WORKER(core_id) {
                enabled_core_ids[num_cores] = core_id;
                num_cores++;
        }
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