#include "test.h"
/* Check condition and return an error if true. */
-#define TEST_RCU_MAX_LCORE 128
-static uint16_t enabled_core_ids[TEST_RCU_MAX_LCORE];
-static uint8_t num_cores;
+static uint16_t enabled_core_ids[RTE_MAX_LCORE];
+static unsigned int num_cores;
static uint32_t *keys;
#define TOTAL_ENTRY (1024 * 8)
static volatile uint8_t all_registered;
static volatile uint32_t thr_id;
-static struct rte_rcu_qsbr *t[TEST_RCU_MAX_LCORE];
+static struct rte_rcu_qsbr *t[RTE_MAX_LCORE];
static struct rte_hash *h;
static char hash_name[8];
-static rte_atomic64_t updates, checks;
-static rte_atomic64_t update_cycles, check_cycles;
+static uint64_t updates, checks;
+static uint64_t update_cycles, check_cycles;
/* Scale down results to 1000 operations to support lower
* granularity clocks.
*/
#define RCU_SCALE_DOWN 1000
-/* Simple way to allocate thread ids in 0 to TEST_RCU_MAX_LCORE space */
+/* Simple way to allocate thread ids in 0 to RTE_MAX_LCORE space */
static inline uint32_t
alloc_thread_id(void)
{
uint32_t tmp_thr_id;
tmp_thr_id = __atomic_fetch_add(&thr_id, 1, __ATOMIC_RELAXED);
- if (tmp_thr_id >= TEST_RCU_MAX_LCORE)
+ if (tmp_thr_id >= RTE_MAX_LCORE)
printf("Invalid thread id %u\n", tmp_thr_id);
return tmp_thr_id;
}
-static inline int
-get_enabled_cores_mask(void)
-{
- uint16_t core_id;
- uint32_t max_cores = rte_lcore_count();
-
- if (max_cores > TEST_RCU_MAX_LCORE) {
- printf("Number of cores exceed %d\n", TEST_RCU_MAX_LCORE);
- return -1;
- }
-
- core_id = 0;
- num_cores = 0;
- RTE_LCORE_FOREACH_SLAVE(core_id) {
- enabled_core_ids[num_cores] = core_id;
- num_cores++;
- }
-
- return 0;
-}
-
static int
test_rcu_qsbr_reader_perf(void *arg)
{
}
cycles = rte_rdtsc_precise() - begin;
- rte_atomic64_add(&update_cycles, cycles);
- rte_atomic64_add(&updates, loop_cnt);
+ __atomic_fetch_add(&update_cycles, cycles, __ATOMIC_RELAXED);
+ __atomic_fetch_add(&updates, loop_cnt, __ATOMIC_RELAXED);
/* Make the thread offline */
rte_rcu_qsbr_thread_offline(t[0], thread_id);
} while (loop_cnt < 20000000);
cycles = rte_rdtsc_precise() - begin;
- rte_atomic64_add(&check_cycles, cycles);
- rte_atomic64_add(&checks, loop_cnt);
+ __atomic_fetch_add(&check_cycles, cycles, __ATOMIC_RELAXED);
+ __atomic_fetch_add(&checks, loop_cnt, __ATOMIC_RELAXED);
return 0;
}
static int
test_rcu_qsbr_perf(void)
{
- int i, sz;
- int tmp_num_cores;
+ size_t sz;
+ unsigned int i, tmp_num_cores;
writer_done = 0;
- rte_atomic64_clear(&updates);
- rte_atomic64_clear(&update_cycles);
- rte_atomic64_clear(&checks);
- rte_atomic64_clear(&check_cycles);
+ __atomic_store_n(&updates, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&checks, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);
printf("\nPerf Test: %d Readers/1 Writer('wait' in qsbr_check == true)\n",
num_cores - 1);
if (all_registered == 1)
tmp_num_cores = num_cores - 1;
else
- tmp_num_cores = TEST_RCU_MAX_LCORE;
+ tmp_num_cores = RTE_MAX_LCORE;
sz = rte_rcu_qsbr_get_memsize(tmp_num_cores);
t[0] = (struct rte_rcu_qsbr *)rte_zmalloc("rcu0", sz,
/* Wait until all readers have exited */
rte_eal_mp_wait_lcore();
- printf("Total RCU updates = %"PRIi64"\n", rte_atomic64_read(&updates));
- printf("Cycles per %d updates: %"PRIi64"\n", RCU_SCALE_DOWN,
- rte_atomic64_read(&update_cycles) /
- (rte_atomic64_read(&updates) / RCU_SCALE_DOWN));
- printf("Total RCU checks = %"PRIi64"\n", rte_atomic64_read(&checks));
+ printf("Total quiescent state updates = %"PRIi64"\n",
+ __atomic_load_n(&updates, __ATOMIC_RELAXED));
+ printf("Cycles per %d quiescent state updates: %"PRIi64"\n",
+ RCU_SCALE_DOWN,
+ __atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /
+ (__atomic_load_n(&updates, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));
+ printf("Total RCU checks = %"PRIi64"\n", __atomic_load_n(&checks, __ATOMIC_RELAXED));
printf("Cycles per %d checks: %"PRIi64"\n", RCU_SCALE_DOWN,
- rte_atomic64_read(&check_cycles) /
- (rte_atomic64_read(&checks) / RCU_SCALE_DOWN));
+ __atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /
+ (__atomic_load_n(&checks, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));
rte_free(t[0]);
static int
test_rcu_qsbr_rperf(void)
{
- int i, sz;
- int tmp_num_cores;
+ size_t sz;
+ unsigned int i, tmp_num_cores;
- rte_atomic64_clear(&updates);
- rte_atomic64_clear(&update_cycles);
+ __atomic_store_n(&updates, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);
__atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);
if (all_registered == 1)
tmp_num_cores = num_cores;
else
- tmp_num_cores = TEST_RCU_MAX_LCORE;
+ tmp_num_cores = RTE_MAX_LCORE;
sz = rte_rcu_qsbr_get_memsize(tmp_num_cores);
t[0] = (struct rte_rcu_qsbr *)rte_zmalloc("rcu0", sz,
/* Wait until all readers have exited */
rte_eal_mp_wait_lcore();
- printf("Total RCU updates = %"PRIi64"\n", rte_atomic64_read(&updates));
- printf("Cycles per %d updates: %"PRIi64"\n", RCU_SCALE_DOWN,
- rte_atomic64_read(&update_cycles) /
- (rte_atomic64_read(&updates) / RCU_SCALE_DOWN));
+ printf("Total quiescent state updates = %"PRIi64"\n",
+ __atomic_load_n(&updates, __ATOMIC_RELAXED));
+ printf("Cycles per %d quiescent state updates: %"PRIi64"\n",
+ RCU_SCALE_DOWN,
+ __atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /
+ (__atomic_load_n(&updates, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));
rte_free(t[0]);
static int
test_rcu_qsbr_wperf(void)
{
- int i, sz;
+ size_t sz;
+ unsigned int i;
- rte_atomic64_clear(&checks);
- rte_atomic64_clear(&check_cycles);
+ __atomic_store_n(&checks, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);
__atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);
/* Number of readers does not matter for QS variable in this test
* case as no reader will be registered.
*/
- sz = rte_rcu_qsbr_get_memsize(TEST_RCU_MAX_LCORE);
+ sz = rte_rcu_qsbr_get_memsize(RTE_MAX_LCORE);
t[0] = (struct rte_rcu_qsbr *)rte_zmalloc("rcu0", sz,
RTE_CACHE_LINE_SIZE);
/* QS variable is initialized */
- rte_rcu_qsbr_init(t[0], TEST_RCU_MAX_LCORE);
+ rte_rcu_qsbr_init(t[0], RTE_MAX_LCORE);
/* Writer threads are launched */
for (i = 0; i < num_cores; i++)
/* Wait until all readers have exited */
rte_eal_mp_wait_lcore();
- printf("Total RCU checks = %"PRIi64"\n", rte_atomic64_read(&checks));
+ printf("Total RCU checks = %"PRIi64"\n", __atomic_load_n(&checks, __ATOMIC_RELAXED));
printf("Cycles per %d checks: %"PRIi64"\n", RCU_SCALE_DOWN,
- rte_atomic64_read(&check_cycles) /
- (rte_atomic64_read(&checks) / RCU_SCALE_DOWN));
+ __atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /
+ (__atomic_load_n(&checks, __ATOMIC_RELAXED) / RCU_SCALE_DOWN));
rte_free(t[0]);
} while (!writer_done);
cycles = rte_rdtsc_precise() - begin;
- rte_atomic64_add(&update_cycles, cycles);
- rte_atomic64_add(&updates, loop_cnt);
+ __atomic_fetch_add(&update_cycles, cycles, __ATOMIC_RELAXED);
+ __atomic_fetch_add(&updates, loop_cnt, __ATOMIC_RELAXED);
rte_rcu_qsbr_thread_unregister(temp, thread_id);
for (i = 0; i < TOTAL_ENTRY; i++) {
hash_data[i] = rte_zmalloc(NULL,
- sizeof(uint32_t) * TEST_RCU_MAX_LCORE, 0);
+ sizeof(uint32_t) * RTE_MAX_LCORE, 0);
if (hash_data[i] == NULL) {
printf("No memory\n");
return NULL;
test_rcu_qsbr_sw_sv_1qs(void)
{
uint64_t token, begin, cycles;
- int i, j, tmp_num_cores, sz;
+ size_t sz;
+ unsigned int i, j, tmp_num_cores;
int32_t pos;
writer_done = 0;
- rte_atomic64_clear(&updates);
- rte_atomic64_clear(&update_cycles);
- rte_atomic64_clear(&checks);
- rte_atomic64_clear(&check_cycles);
+ __atomic_store_n(&updates, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&checks, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);
__atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);
if (all_registered == 1)
tmp_num_cores = num_cores;
else
- tmp_num_cores = TEST_RCU_MAX_LCORE;
+ tmp_num_cores = RTE_MAX_LCORE;
sz = rte_rcu_qsbr_get_memsize(tmp_num_cores);
t[0] = (struct rte_rcu_qsbr *)rte_zmalloc("rcu0", sz,
}
cycles = rte_rdtsc_precise() - begin;
- rte_atomic64_add(&check_cycles, cycles);
- rte_atomic64_add(&checks, i);
+ __atomic_fetch_add(&check_cycles, cycles, __ATOMIC_RELAXED);
+ __atomic_fetch_add(&checks, i, __ATOMIC_RELAXED);
writer_done = 1;
rte_free(keys);
printf("Following numbers include calls to rte_hash functions\n");
- printf("Cycles per 1 update(online/update/offline): %"PRIi64"\n",
- rte_atomic64_read(&update_cycles) /
- rte_atomic64_read(&updates));
+ printf("Cycles per 1 quiescent state update(online/update/offline): %"PRIi64"\n",
+ __atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /
+ __atomic_load_n(&updates, __ATOMIC_RELAXED));
printf("Cycles per 1 check(start, check): %"PRIi64"\n\n",
- rte_atomic64_read(&check_cycles) /
- rte_atomic64_read(&checks));
+ __atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /
+ __atomic_load_n(&checks, __ATOMIC_RELAXED));
rte_free(t[0]);
test_rcu_qsbr_sw_sv_1qs_non_blocking(void)
{
uint64_t token, begin, cycles;
- int i, j, ret, tmp_num_cores, sz;
+ int ret;
+ size_t sz;
+ unsigned int i, j, tmp_num_cores;
int32_t pos;
writer_done = 0;
printf("Perf test: 1 writer, %d readers, 1 QSBR variable, 1 QSBR Query, Non-Blocking QSBR check\n", num_cores);
- __atomic_store_n(&thr_id, 0, __ATOMIC_SEQ_CST);
+ __atomic_store_n(&thr_id, 0, __ATOMIC_RELAXED);
if (all_registered == 1)
tmp_num_cores = num_cores;
else
- tmp_num_cores = TEST_RCU_MAX_LCORE;
+ tmp_num_cores = RTE_MAX_LCORE;
sz = rte_rcu_qsbr_get_memsize(tmp_num_cores);
t[0] = (struct rte_rcu_qsbr *)rte_zmalloc("rcu0", sz,
}
cycles = rte_rdtsc_precise() - begin;
- rte_atomic64_add(&check_cycles, cycles);
- rte_atomic64_add(&checks, i);
+ __atomic_fetch_add(&check_cycles, cycles, __ATOMIC_RELAXED);
+ __atomic_fetch_add(&checks, i, __ATOMIC_RELAXED);
writer_done = 1;
/* Wait and check return value from reader threads */
rte_free(keys);
printf("Following numbers include calls to rte_hash functions\n");
- printf("Cycles per 1 update(online/update/offline): %"PRIi64"\n",
- rte_atomic64_read(&update_cycles) /
- rte_atomic64_read(&updates));
+ printf("Cycles per 1 quiescent state update(online/update/offline): %"PRIi64"\n",
+ __atomic_load_n(&update_cycles, __ATOMIC_RELAXED) /
+ __atomic_load_n(&updates, __ATOMIC_RELAXED));
printf("Cycles per 1 check(start, check): %"PRIi64"\n\n",
- rte_atomic64_read(&check_cycles) /
- rte_atomic64_read(&checks));
+ __atomic_load_n(&check_cycles, __ATOMIC_RELAXED) /
+ __atomic_load_n(&checks, __ATOMIC_RELAXED));
rte_free(t[0]);
static int
test_rcu_qsbr_main(void)
{
- rte_atomic64_init(&updates);
- rte_atomic64_init(&update_cycles);
- rte_atomic64_init(&checks);
- rte_atomic64_init(&check_cycles);
+ uint16_t core_id;
- if (get_enabled_cores_mask() != 0)
- return -1;
+ if (RTE_EXEC_ENV_IS_WINDOWS)
+ return TEST_SKIPPED;
- printf("Number of cores provided = %d\n", num_cores);
- if (num_cores < 2) {
- printf("Test failed! Need 2 or more cores\n");
- goto test_fail;
+ if (rte_lcore_count() < 3) {
+ printf("Not enough cores for rcu_qsbr_perf_autotest, expecting at least 3\n");
+ return TEST_SKIPPED;
}
- if (num_cores > TEST_RCU_MAX_LCORE) {
- printf("Test failed! %d cores supported\n", TEST_RCU_MAX_LCORE);
- goto test_fail;
+
+ __atomic_store_n(&updates, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&update_cycles, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&checks, 0, __ATOMIC_RELAXED);
+ __atomic_store_n(&check_cycles, 0, __ATOMIC_RELAXED);
+
+ num_cores = 0;
+ RTE_LCORE_FOREACH_WORKER(core_id) {
+ enabled_core_ids[num_cores] = core_id;
+ num_cores++;
}
+ printf("Number of cores provided = %d\n", num_cores);
printf("Perf test with all reader threads registered\n");
printf("--------------------------------------------\n");
all_registered = 1;
goto test_fail;
/* Make sure the actual number of cores provided is less than
- * TEST_RCU_MAX_LCORE. This will allow for some threads not
+ * RTE_MAX_LCORE. This will allow for some threads not
* to be registered on the QS variable.
*/
- if (num_cores >= TEST_RCU_MAX_LCORE) {
+ if (num_cores >= RTE_MAX_LCORE) {
printf("Test failed! number of cores provided should be less than %d\n",
- TEST_RCU_MAX_LCORE);
+ RTE_MAX_LCORE);
goto test_fail;
}
git.droids-corp.org / dpdk.git / blobdiff