net/mlx5: support match on IPv4 TTL and IPv6 HLIM

[dpdk.git] / app / test-crypto-perf / cperf_test_latency.c

diff --git a/app/test-crypto-perf/cperf_test_latency.c b/app/test-crypto-perf/cperf_test_latency.c
index ca2a4ba..0e4d0e1 100644 (file)
--- a/app/test-crypto-perf/cperf_test_latency.c
+++ b/app/test-crypto-perf/cperf_test_latency.c
@@ -1,33 +1,5 @@
-/*-
- *   BSD LICENSE
- *
- *   Copyright(c) 2016-2017 Intel Corporation. All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2016-2017 Intel Corporation
  */
 
 #include <rte_malloc.h>
@@ -68,9 +40,6 @@ struct priv_op_data {
        struct cperf_op_result *result;
 };
 
-#define max(a, b) (a > b ? (uint64_t)a : (uint64_t)b)
-#define min(a, b) (a < b ? (uint64_t)a : (uint64_t)b)
-
 static void
 cperf_latency_test_free(struct cperf_latency_ctx *ctx)
 {
@@ -90,6 +59,7 @@ cperf_latency_test_free(struct cperf_latency_ctx *ctx)
 
 void *
 cperf_latency_test_constructor(struct rte_mempool *sess_mp,
+               struct rte_mempool *sess_priv_mp,
                uint8_t dev_id, uint16_t qp_id,
                const struct cperf_options *options,
                const struct cperf_test_vector *test_vector,
@@ -114,8 +84,8 @@ cperf_latency_test_constructor(struct rte_mempool *sess_mp,
                sizeof(struct rte_crypto_sym_op) +
                sizeof(struct cperf_op_result *);
 
-       ctx->sess = op_fns->sess_create(sess_mp, dev_id, options, test_vector,
-                       iv_offset);
+       ctx->sess = op_fns->sess_create(sess_mp, sess_priv_mp, dev_id, options,
+                       test_vector, iv_offset);
        if (ctx->sess == NULL)
                goto err;
 
@@ -154,8 +124,9 @@ cperf_latency_test_runner(void *arg)
        struct cperf_latency_ctx *ctx = arg;
        uint16_t test_burst_size;
        uint8_t burst_size_idx = 0;
+       uint32_t imix_idx = 0;
 
-       static int only_once;
+       static rte_atomic16_t display_once = RTE_ATOMIC16_INIT(0);
 
        if (ctx == NULL)
                return 0;
@@ -218,7 +189,7 @@ cperf_latency_test_runner(void *arg)
                                                burst_size) != 0) {
                                RTE_LOG(ERR, USER1,
                                        "Failed to allocate more crypto operations "
-                                       "from the the crypto operation pool.\n"
+                                       "from the crypto operation pool.\n"
                                        "Consider increasing the pool size "
                                        "with --pool-sz\n");
                                return -1;
@@ -228,7 +199,8 @@ cperf_latency_test_runner(void *arg)
                        (ctx->populate_ops)(ops, ctx->src_buf_offset,
                                        ctx->dst_buf_offset,
                                        burst_size, ctx->sess, ctx->options,
-                                       ctx->test_vector, iv_offset);
+                                       ctx->test_vector, iv_offset,
+                                       &imix_idx);
 
                        tsc_start = rte_rdtsc_precise();
 
@@ -279,13 +251,13 @@ cperf_latency_test_runner(void *arg)
                                                (void **)ops_processed, ops_deqd);
 
                                deqd_tot += ops_deqd;
-                               deqd_max = max(ops_deqd, deqd_max);
-                               deqd_min = min(ops_deqd, deqd_min);
+                               deqd_max = RTE_MAX(ops_deqd, deqd_max);
+                               deqd_min = RTE_MIN(ops_deqd, deqd_min);
                        }
 
                        enqd_tot += ops_enqd;
-                       enqd_max = max(ops_enqd, enqd_max);
-                       enqd_min = min(ops_enqd, enqd_min);
+                       enqd_max = RTE_MAX(ops_enqd, enqd_max);
+                       enqd_min = RTE_MIN(ops_enqd, enqd_min);
 
                        b_idx++;
                }
@@ -309,15 +281,15 @@ cperf_latency_test_runner(void *arg)
                                                (void **)ops_processed, ops_deqd);
 
                                deqd_tot += ops_deqd;
-                               deqd_max = max(ops_deqd, deqd_max);
-                               deqd_min = min(ops_deqd, deqd_min);
+                               deqd_max = RTE_MAX(ops_deqd, deqd_max);
+                               deqd_min = RTE_MIN(ops_deqd, deqd_min);
                        }
                }
 
                for (i = 0; i < tsc_idx; i++) {
                        tsc_val = ctx->res[i].tsc_end - ctx->res[i].tsc_start;
-                       tsc_max = max(tsc_val, tsc_max);
-                       tsc_min = min(tsc_val, tsc_min);
+                       tsc_max = RTE_MAX(tsc_val, tsc_max);
+                       tsc_min = RTE_MIN(tsc_val, tsc_min);
                        tsc_tot += tsc_val;
                }
 
@@ -336,7 +308,7 @@ cperf_latency_test_runner(void *arg)
                time_min = tunit*(double)(tsc_min) / tsc_hz;
 
                if (ctx->options->csv) {
-                       if (!only_once)
+                       if (rte_atomic16_test_and_set(&display_once))
                                printf("\n# lcore, Buffer Size, Burst Size, Pakt Seq #, "
                                                "Packet Size, cycles, time (us)");
 
@@ -351,7 +323,6 @@ cperf_latency_test_runner(void *arg)
                                                / tsc_hz);
 
                        }
-                       only_once = 1;
                } else {
                        printf("\n# Device %d on lcore %u\n", ctx->dev_id,
                                ctx->lcore_id);