uint16_t nb_tx_queue_stats_mappings = 0;
uint16_t nb_rx_queue_stats_mappings = 0;
+/*
+ * Display zero values by default for xstats
+ */
+uint8_t xstats_hide_zero;
+
unsigned int num_sockets = 0;
unsigned int socket_ids[RTE_MAX_NUMA_NODES];
uint8_t gro_flush_cycles = GRO_DEFAULT_FLUSH_CYCLES;
/* Forward function declarations */
-static void map_port_queue_stats_mapping_registers(uint8_t pi, struct rte_port *port);
+static void map_port_queue_stats_mapping_registers(portid_t pi,
+ struct rte_port *port);
static void check_all_ports_link_status(uint32_t port_mask);
static int eth_event_callback(portid_t port_id,
enum rte_eth_event_type type,
}
void
-detach_port(uint8_t port_id)
+detach_port(portid_t port_id)
{
char name[RTE_ETH_NAME_MAX_LEN];
rmv_event_callback(void *arg)
{
struct rte_eth_dev *dev;
- uint8_t port_id = (intptr_t)arg;
+ portid_t port_id = (intptr_t)arg;
RTE_ETH_VALID_PORTID_OR_RET(port_id);
dev = &rte_eth_devices[port_id];
}
static int
-set_tx_queue_stats_mapping_registers(uint8_t port_id, struct rte_port *port)
+set_tx_queue_stats_mapping_registers(portid_t port_id, struct rte_port *port)
{
uint16_t i;
int diag;
}
static int
-set_rx_queue_stats_mapping_registers(uint8_t port_id, struct rte_port *port)
+set_rx_queue_stats_mapping_registers(portid_t port_id, struct rte_port *port)
{
uint16_t i;
int diag;
}
static void
-map_port_queue_stats_mapping_registers(uint8_t pi, struct rte_port *port)
+map_port_queue_stats_mapping_registers(portid_t pi, struct rte_port *port)
{
int diag = 0;
1 << (i % vmdq_rx_conf->nb_queue_pools);
}
for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
- vmdq_rx_conf->dcb_tc[i] = i;
- vmdq_tx_conf->dcb_tc[i] = i;
+ vmdq_rx_conf->dcb_tc[i] = i % num_tcs;
+ vmdq_tx_conf->dcb_tc[i] = i % num_tcs;
}
/* set DCB mode of RX and TX of multiple queues */