net/iavf: add GTPU in default hash

[dpdk.git] / config / x86 / meson.build

diff --git a/config/x86/meson.build b/config/x86/meson.build
index 9e5952a..6ec020e 100644 (file)
--- a/config/x86/meson.build
+++ b/config/x86/meson.build
@@ -1,24 +1,19 @@
 # SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017 Intel Corporation
-
-# for checking defines we need to use the correct compiler flags
-march_opt = ['-march=@0@'.format(machine)]
+# Copyright(c) 2017-2019 Intel Corporation
 
 # get binutils version for the workaround of Bug 97
-ldver = run_command('ld', '-v').stdout().strip()
-if ldver.contains('2.30')
-       if cc.has_argument('-mno-avx512f')
-               march_opt += '-mno-avx512f'
-               message('Binutils 2.30 detected, disabling AVX512 support as workaround for bug #97')
+if not is_windows
+       binutils_ok = run_command(binutils_avx512_check)
+       if binutils_ok.returncode() != 0 and cc.has_argument('-mno-avx512f')
+               machine_args += '-mno-avx512f'
+               warning('Binutils error with AVX512 assembly, disabling AVX512 support')
        endif
 endif
 
 # we require SSE4.2 for DPDK
-sse_errormsg = '''SSE4.2 instruction set is required for DPDK.
-Please set the machine type to "nehalem" or "corei7" or higher value'''
-
-if cc.get_define('__SSE4_2__', args: march_opt) == ''
-       error(sse_errormsg)
+if cc.get_define('__SSE4_2__', args: machine_args) == ''
+       message('SSE 4.2 not enabled by default, explicitly enabling')
+       machine_args += '-msse4'
 endif
 
 base_flags = ['SSE', 'SSE2', 'SSE3','SSSE3', 'SSE4_1', 'SSE4_2']
@@ -27,35 +22,29 @@ foreach f:base_flags
        compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
 endforeach
 
+optional_flags = ['AES', 'PCLMUL',
+               'AVX', 'AVX2', 'AVX512F',
+               'RDRND', 'RDSEED']
+foreach f:optional_flags
+       if cc.get_define('__@0@__'.format(f), args: machine_args) == '1'
+               if f == 'PCLMUL' # special case flags with different defines
+                       f = 'PCLMULQDQ'
+               elif f == 'RDRND'
+                       f = 'RDRAND'
+               endif
+               dpdk_conf.set('RTE_MACHINE_CPUFLAG_' + f, 1)
+               compile_time_cpuflags += ['RTE_CPUFLAG_' + f]
+       endif
+endforeach
+
+
 dpdk_conf.set('RTE_ARCH_X86', 1)
-if (host_machine.cpu_family() == 'x86_64')
+if dpdk_conf.get('RTE_ARCH_64')
        dpdk_conf.set('RTE_ARCH_X86_64', 1)
        dpdk_conf.set('RTE_ARCH', 'x86_64')
-       dpdk_conf.set('RTE_ARCH_64', 1)
 else
        dpdk_conf.set('RTE_ARCH_I686', 1)
        dpdk_conf.set('RTE_ARCH', 'i686')
 endif
 
-if cc.get_define('__AES__', args: march_opt) != ''
-       dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1)
-       compile_time_cpuflags += ['RTE_CPUFLAG_AES']
-endif
-if cc.get_define('__PCLMUL__', args: march_opt) != ''
-       dpdk_conf.set('RTE_MACHINE_CPUFLAG_PCLMULQDQ', 1)
-       compile_time_cpuflags += ['RTE_CPUFLAG_PCLMULQDQ']
-endif
-if cc.get_define('__AVX__', args: march_opt) != ''
-       dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX', 1)
-       compile_time_cpuflags += ['RTE_CPUFLAG_AVX']
-endif
-if cc.get_define('__AVX2__', args: march_opt) != ''
-       dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX2', 1)
-       compile_time_cpuflags += ['RTE_CPUFLAG_AVX2']
-endif
-if cc.get_define('__AVX512F__', args: march_opt) != ''
-       dpdk_conf.set('RTE_MACHINE_CPUFLAG_AVX512F', 1)
-       compile_time_cpuflags += ['RTE_CPUFLAG_AVX512F']
-endif
-
 dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)