event/dlb: add infos get and configure

[dpdk.git] / doc / guides / bbdevs / fpga_5gnr_fec.rst

diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst
index 6760391..61c19c3 100644 (file)
--- a/doc/guides/bbdevs/fpga_5gnr_fec.rst
+++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst
@@ -51,10 +51,7 @@ FPGA 5GNR FEC does not support the following:
 Installation
 ------------
 
-Section 3 of the DPDK manual provides instructions on installing and compiling DPDK. The
-default set of bbdev compile flags may be found in config/common_base, where for example
-the flag to build the FPGA 5GNR FEC device, ``CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC``,
-is already set.
+Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
 
 DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
 The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
@@ -93,8 +90,7 @@ the UIO driver by repeating this command for every function.
 
 .. code-block:: console
 
-  cd <dpdk-top-level-directory>
-  insmod ./build/kmod/igb_uio.ko
+  insmod igb_uio.ko
   echo "8086 0d8f" > /sys/bus/pci/drivers/igb_uio/new_id
   lspci -vd8086:0d8f
 
@@ -170,12 +166,12 @@ queues, priorities, load balance, bandwidth and other settings necessary for the
 device to perform FEC functions.
 
 This configuration needs to be executed at least once after reboot or PCI FLR and can
-be achieved by using the function ``fpga_5gnr_fec_configure()``, which sets up the
-parameters defined in ``fpga_5gnr_fec_conf`` structure:
+be achieved by using the function ``rte_fpga_5gnr_fec_configure()``, which sets up the
+parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:
 
 .. code-block:: c
 
-  struct fpga_5gnr_fec_conf {
+  struct rte_fpga_5gnr_fec_conf {
       bool pf_mode_en;
       uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];
       uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];
@@ -214,15 +210,15 @@ parameters defined in ``fpga_5gnr_fec_conf`` structure:
   the FLR time out then set this setting to 0x262=610.
 
 
-An example configuration code calling the function ``fpga_5gnr_fec_configure()`` is shown
+An example configuration code calling the function ``rte_fpga_5gnr_fec_configure()`` is shown
 below:
 
 .. code-block:: c
 
-  struct fpga_5gnr_fec_conf conf;
+  struct rte_fpga_5gnr_fec_conf conf;
   unsigned int i;
 
-  memset(&conf, 0, sizeof(struct fpga_5gnr_fec_conf));
+  memset(&conf, 0, sizeof(struct rte_fpga_5gnr_fec_conf));
   conf.pf_mode_en = 1;
 
   for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {
@@ -235,7 +231,7 @@ below:
   conf.ul_load_balance = 64;
 
   /* setup FPGA PF */
-  ret = fpga_5gnr_fec_configure(info->dev_name, &conf);
+  ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf);
   TEST_ASSERT_SUCCESS(ret,
       "Failed to configure 4G FPGA PF for bbdev %s",
       info->dev_name);