doc: add limitation for ConnectX-4 with L2 in mlx5 guide

[dpdk.git] / doc / guides / nics / mlx5.rst

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 97a144d..5b4bb13 100644 (file)
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -109,6 +109,7 @@ Features
 - Flow metering, including meter policy API.
 - Flow integrity offload API.
 - Connection tracking.
+- Sub-Function representors.
 
 Limitations
 -----------
@@ -123,6 +124,11 @@ Limitations
     - IPv4/UDP with CVLAN filtering
     - Unicast MAC filtering
 
+  - Additional rules are supported from WinOF2 version 2.70:
+
+    - IPv4/TCP with CVLAN filtering
+    - L4 steering rules for port RSS of UDP, TCP and IP
+
 - For secondary process:
 
   - Forked secondary process not supported.
@@ -437,6 +443,9 @@ Limitations
 - Connection tracking:
 
   - Cannot co-exist with ASO meter, ASO age action in a single flow rule.
+  - Flow rules insertion rate and memory consumption need more optimization.
+  - 256 ports maximum.
+  - 4M connections maximum.
 
 Statistics
 ----------
@@ -691,6 +700,13 @@ Driver options
   it is not recommended and may prevent NIC from sending packets over
   some configurations.
 
+  For ConnectX-4 and ConnectX-4 Lx NICs, automatically configured value
+  is insufficient for some traffic, because they require at least all L2 headers
+  to be inlined. For example, Q-in-Q adds 4 bytes to default 18 bytes
+  of Ethernet and VLAN, thus ``txq_inline_min`` must be set to 22.
+  MPLS would add 4 bytes per label. Final value must account for all possible
+  L2 encapsulation headers used in particular environment.
+
   Please, note, this minimal data inlining disengages eMPW feature (Enhanced
   Multi-Packet Write), because last one does not support partial packet inlining.
   This is not very critical due to minimal data inlining is mostly required
@@ -1434,9 +1450,10 @@ the DPDK application.
 
         echo switchdev > /sys/class/net/<net device>/compat/devlink/mode
 
-SubFunction representor support
--------------------------------
-SubFunction is a portion of the PCI device, a SF netdev has its own
+Sub-Function representor
+------------------------
+
+Sub-Function is a portion of the PCI device, a SF netdev has its own
 dedicated queues(txq, rxq). A SF netdev supports E-Switch representation
 offload similar to existing PF and VF representors. A SF shares PCI
 level resources with other SFs and/or with its parent PCI function.
@@ -1491,7 +1508,7 @@ Performance tuning
    for better performance. For VMs, verify that the right CPU
    and NUMA node are pinned according to the above. Run::
 
-        lstopo-no-graphics
+        lstopo-no-graphics --merge
 
    to identify the NUMA node to which the PCIe adapter is connected.