net/octeontx2: support HIGIG2

[dpdk.git] / doc / guides / nics / octeontx2.rst

diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst
index 3b567a55e88f3038ba5742377fb7b3f1d5df8f76..eb7aaa468f68623ea3bd585e9854aa9a0999550b 100644 (file)
--- a/doc/guides/nics/octeontx2.rst
+++ b/doc/guides/nics/octeontx2.rst
@@ -170,6 +170,18 @@ Runtime Config Options
    With the above configuration, each send queue's decscriptor buffer count is
    limited to a maximum of 64 buffers.
 
+- ``switch header enable`` (default ``none``)
+
+   A port can be configured to a specific switch header type by using
+   ``switch_header`` ``devargs`` parameter.
+
+   For example::
+
+      -w 0002:02:00.0,switch_header="higig2"
+
+   With the above configuration, higig2 will be enabled on that port and the
+   traffic on this port should be higig2 traffic only. Supported switch header
+   types are "higig2" and "dsa".
 
 .. note::
 
@@ -188,8 +200,8 @@ The OCTEON TX2 SoC family NIC has inbuilt HW assisted external mempool manager.
 as it is performance wise most effective way for packet allocation and Tx buffer
 recycling on OCTEON TX2 SoC platform.
 
-CRC striping
-~~~~~~~~~~~~
+CRC stripping
+~~~~~~~~~~~~~
 
 The OCTEON TX2 SoC family NICs strip the CRC for every packet being received by
 the host interface irrespective of the offload configuration.
@@ -276,6 +288,8 @@ Patterns:
    +----+--------------------------------+
    | 23 | RTE_FLOW_ITEM_TYPE_GRE_KEY     |
    +----+--------------------------------+
+   | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2      |
+   +----+--------------------------------+
 
 .. note::