Quota and Watermark Sample Application
======================================
-The Quota and Watermark sample application is a simple example of packet processing using Intel® Data Plane Development Kit (Intel® DPDK) that
+The Quota and Watermark sample application is a simple example of packet processing using Data Plane Development Kit (DPDK) that
showcases the use of a quota as the maximum number of packets enqueue/dequeue at a time and low and high watermarks
to signal low and high ring usage respectively.
The MAC addresses of the forwarded Ethernet frames are not affected.
Internally, packets are pulled from the ports by the master logical core and put on a variable length processing pipeline,
-each stage of which being connected by rings, as shown in Figure 12.
+each stage of which being connected by rings, as shown in :numref:`figure_pipeline_overview`.
-.. _figure_12:
+.. _figure_pipeline_overview:
-**Figure 12. Pipeline Overview**
+.. figure:: img/pipeline_overview.*
-.. image15_png has been renamed
+ Pipeline Overview
-|pipeline_overview|
An adjustable quota value controls how many packets are being moved through the pipeline per enqueue and dequeue.
Adjustable watermark values associated with the rings control a back-off mechanism that
On top of serving as an example of quota and watermark usage,
this application can be used to benchmark ring based processing pipelines performance using a traffic- generator,
-as shown in Figure 13.
+as shown in :numref:`figure_ring_pipeline_perf_setup`.
-.. _figure_13:
+.. _figure_ring_pipeline_perf_setup:
-**Figure 13. Ring-based Processing Pipeline Performance Setup**
+.. figure:: img/ring_pipeline_perf_setup.*
-.. image16_png has been renamed
+ Ring-based Processing Pipeline Performance Setup
-|ring_pipeline_perf_setup|
Compiling the Application
-------------------------
export RTE_TARGET=x86_64-native-linuxapp-gcc
- See the *Intel® DPDK Getting Started Guide* for possible RTE_TARGET values.
+ See the *DPDK Getting Started Guide* for possible RTE_TARGET values.
#. Build the application:
./qw/build/qw -c f -n 4 -- -p 5
-Refer to the *Intel® DPDK Getting Started Guide* for general information on running applications and
+Refer to the *DPDK Getting Started Guide* for general information on running applications and
the Environment Abstraction Layer (EAL) options.
Running the Control Application
./qwctl/build/qwctl -c 1 -n 4 --proc-type=secondary
-Refer to the *Intel® DPDK Getting Started* Guide for general information on running applications and
+Refer to the *DPDK Getting Started* Guide for general information on running applications and
the Environment Abstraction Layer (EAL) options.
qwctl is an interactive command line that let the user change variables in a running instance of qw.
rte_exit(EXIT_FAILURE, "rte_eal_pci_probe(): error %d\n", ret);
if (rte_eth_dev_count() < 2)
- rte_exit(EXIT_FAILURE, "Not enough ethernet port available\n");
+ rte_exit(EXIT_FAILURE, "Not enough Ethernet port available\n");
}
To fully understand this code, it is recommended to study the chapters that relate to the *Poll Mode Driver*
-in the *Intel® DPDK Getting Started Guide* and the *Intel® DPDK API Reference*.
+in the *DPDK Getting Started Guide* and the *DPDK API Reference*.
Shared Variables Setup
^^^^^^^^^^^^^^^^^^^^^^
pair_ports();
The configure_eth_port() and init_ring() functions are used to configure a port and a ring respectively and are defined in init.c.
-They make use of the Intel® DPDK APIs defined in rte_eth.h and rte_ring.h.
+They make use of the DPDK APIs defined in rte_eth.h and rte_ring.h.
pair_ports() builds the port_pairs[] array so that its key-value pairs are a mapping between reception and transmission ports.
It is defined in init.c.
The application uses the master logical core to poll all the ports for new packets and enqueue them on a ring associated with the port.
Each logical core except the last runs pipeline_stage() after a ring for each used port is initialized on that core.
-pipeline_stage() on core X dequeues packets from core X-1's rings and enqueue them on its own rings. See Figure 14.
+pipeline_stage() on core X dequeues packets from core X-1's rings and enqueue them on its own rings. See :numref:`figure_threads_pipelines`.
.. code-block:: c
Receive, Process and Transmit Packets
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. _figure_14:
+.. _figure_threads_pipelines:
-Figure 14 shows where each thread in the pipeline is.
-It should be used as a reference while reading the rest of this section.
+.. figure:: img/threads_pipelines.*
-**Figure 14. Threads and Pipelines**
+ Threads and Pipelines
-.. image17_png has been renamed
-
-|threads_pipelines|
In the receive_stage() function running on the master logical core,
the main task is to read ingress packets from the RX ports and enqueue them
qw_memzone = rte_memzone_lookup(QUOTA_WATERMARK_MEMZONE_NAME);
if (qw_memzone == NULL)
- rte_exit(EXIT_FAILURE, "Could't find memzone\n");
+ rte_exit(EXIT_FAILURE, "Couldn't find memzone\n");
quota = qw_memzone->addr;
low_watermark = (unsigned int *) qw_memzone->addr + sizeof(int);
}
-
-.. |pipeline_overview| image:: img/pipeline_overview.png
-
-.. |ring_pipeline_perf_setup| image:: img/ring_pipeline_perf_setup.png
-
-.. |threads_pipelines| image:: img/threads_pipelines.png
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