#define ACC100_RESET_HARD 0x1FF
#define ACC100_ENGINES_MAX 9
#define ACC100_LONG_WAIT 1000
+#define ACC100_GPEX_AXIMAP_NUM 17
/* ACC100 DMA Descriptor triplet */
struct acc100_dma_triplet {
rte_iova_t sw_rings_iova; /* IOVA address of sw_rings */
/* Virtual address of the info memory routed to the this function under
* operation, whether it is PF or VF.
+ * HW may DMA information data at this location asynchronously
*/
+ union acc100_info_ring_data *info_ring;
+
union acc100_harq_layout_data *harq_layout;
+ /* Virtual Info Ring head */
+ uint16_t info_ring_head;
+ /* Number of bytes available for each queue in device, depending on
+ * how many queues are enabled with configure()
+ */
uint32_t sw_ring_size;
uint32_t ddr_size; /* Size in kB */
uint32_t *tail_ptrs; /* Base address of response tail pointer buffer */
bool configured; /**< True if this ACC100 device is configured */
};
+/**
+ * Structure with details about RTE_BBDEV_EVENT_DEQUEUE event. It's passed to
+ * the callback function.
+ */
+struct acc100_deq_intr_details {
+ uint16_t queue_id;
+};
+
#endif /* _RTE_ACC100_PMD_H_ */