#define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8
#define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8
+/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
+#define N_ZC_1 66 /* N = 66 Zc for BG 1 */
+#define N_ZC_2 50 /* N = 50 Zc for BG 2 */
+#define K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */
+#define K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */
+#define K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */
+#define K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */
+#define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */
+#define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */
/* FPGA 5GNR FEC Register mapping on BAR0 */
enum {
struct fpga_5gnr_fec_device {
/** Base address of MMIO registers (BAR0) */
void *mmio_base;
+ /** Base address of memory for sw rings */
+ void *sw_rings;
+ /** Physical address of sw_rings */
+ rte_iova_t sw_rings_phys;
+ /** Number of bytes available for each queue in device. */
+ uint32_t sw_ring_size;
+ /** Max number of entries available for each queue in device */
+ uint32_t sw_ring_max_depth;
+ /** Base address of response tail pointer buffer */
+ uint32_t *tail_ptrs;
+ /** Physical address of tail pointers */
+ rte_iova_t tail_ptr_phys;
+ /** Queues flush completion flag */
+ uint64_t *flush_queue_status;
+ /* Bitmap capturing which Queues are bound to the PF/VF */
+ uint64_t q_bound_bit_map;
+ /* Bitmap capturing which Queues have already been assigned */
+ uint64_t q_assigned_bit_map;
/** True if this is a PF FPGA FEC device */
bool pf_device;
};
+/* Structure associated with each queue. */
+struct __rte_cache_aligned fpga_queue {
+ struct fpga_ring_ctrl_reg ring_ctrl_reg; /* Ring Control Register */
+ union fpga_dma_desc *ring_addr; /* Virtual address of software ring */
+ uint64_t *ring_head_addr; /* Virtual address of completion_head */
+ uint64_t shadow_completion_head; /* Shadow completion head value */
+ uint16_t head_free_desc; /* Ring head */
+ uint16_t tail; /* Ring tail */
+ /* Mask used to wrap enqueued descriptors on the sw ring */
+ uint32_t sw_ring_wrap_mask;
+ uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */
+ uint8_t q_idx; /* Queue index */
+ struct fpga_5gnr_fec_device *d;
+ /* MMIO register of shadow_tail used to enqueue descriptors */
+ void *shadow_tail_addr;
+};
+
+/* Write to 16 bit MMIO register address */
+static inline void
+mmio_write_16(void *addr, uint16_t value)
+{
+ *((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value);
+}
+
+/* Write to 32 bit MMIO register address */
+static inline void
+mmio_write_32(void *addr, uint32_t value)
+{
+ *((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value);
+}
+
+/* Write to 64 bit MMIO register address */
+static inline void
+mmio_write_64(void *addr, uint64_t value)
+{
+ *((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value);
+}
+
+/* Write a 8 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload)
+{
+ void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+ *((volatile uint8_t *)(reg_addr)) = payload;
+}
+
+/* Write a 16 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload)
+{
+ void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+ mmio_write_16(reg_addr, payload);
+}
+
+/* Write a 32 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload)
+{
+ void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+ mmio_write_32(reg_addr, payload);
+}
+
+/* Write a 64 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload)
+{
+ void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+ mmio_write_64(reg_addr, payload);
+}
+
+/* Write a ring control register of a FPGA 5GNR FEC device */
+static inline void
+fpga_ring_reg_write(void *mmio_base, uint32_t offset,
+ struct fpga_ring_ctrl_reg payload)
+{
+ fpga_reg_write_64(mmio_base, offset, payload.ring_base_addr);
+ fpga_reg_write_64(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_ADDR,
+ payload.ring_head_addr);
+ fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SIZE,
+ payload.ring_size);
+ fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,
+ payload.head_point);
+ fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN,
+ payload.flush_queue_en);
+ fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,
+ payload.shadow_tail);
+ fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_MISC,
+ payload.misc);
+ fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
+ payload.enable);
+}
+
/* Read a register of FPGA 5GNR FEC device */
static inline uint32_t
fpga_reg_read_32(void *mmio_base, uint32_t offset)
return rte_le_to_cpu_32(ret);
}
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+
+/* Read a register of FPGA 5GNR FEC device */
+static inline uint16_t
+fpga_reg_read_16(void *mmio_base, uint32_t offset)
+{
+ void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+ uint16_t ret = *((volatile uint16_t *)(reg_addr));
+ return rte_le_to_cpu_16(ret);
+}
+
+#endif
+
+/* Read a register of FPGA 5GNR FEC device */
+static inline uint8_t
+fpga_reg_read_8(void *mmio_base, uint32_t offset)
+{
+ void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+ return *((volatile uint8_t *)(reg_addr));
+}
+
+/* Read a register of FPGA 5GNR FEC device */
+static inline uint64_t
+fpga_reg_read_64(void *mmio_base, uint32_t offset)
+{
+ void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+ uint64_t ret = *((volatile uint64_t *)(reg_addr));
+ return rte_le_to_cpu_64(ret);
+}
+
#endif /* _FPGA_5GNR_FEC_H_ */
git.droids-corp.org / dpdk.git / blobdiff