#include "fpga_lte_fec.h"
-/* Turbo SW PMD logging ID */
-static int fpga_lte_fec_logtype;
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+RTE_LOG_REGISTER_DEFAULT(fpga_lte_fec_logtype, DEBUG);
+#else
+RTE_LOG_REGISTER_DEFAULT(fpga_lte_fec_logtype, NOTICE);
+#endif
/* Helper macro for logging */
#define rte_bbdev_log(level, fmt, ...) \
dev_info->default_queue_conf = default_queue_conf;
dev_info->capabilities = bbdev_capabilities;
dev_info->cpu_flag_reqs = NULL;
+ dev_info->data_endianness = RTE_LITTLE_ENDIAN;
/* Calculates number of queues assigned to device */
dev_info->max_num_queues = 0;
* It ensures that callback function assigned to that descriptor will
* invoked when any FPGA queue issues interrupt.
*/
- for (i = 0; i < FPGA_NUM_INTR_VEC; ++i)
- dev->intr_handle->efds[i] = dev->intr_handle->fd;
-
- if (!dev->intr_handle->intr_vec) {
- dev->intr_handle->intr_vec = rte_zmalloc("intr_vec",
- dev->data->num_queues * sizeof(int), 0);
- if (!dev->intr_handle->intr_vec) {
- rte_bbdev_log(ERR, "Failed to allocate %u vectors",
- dev->data->num_queues);
- return -ENOMEM;
- }
+ for (i = 0; i < FPGA_NUM_INTR_VEC; ++i) {
+ if (rte_intr_efds_index_set(dev->intr_handle, i,
+ rte_intr_fd_get(dev->intr_handle)))
+ return -rte_errno;
+ }
+
+ if (rte_intr_vec_list_alloc(dev->intr_handle, "intr_vec",
+ dev->data->num_queues)) {
+ rte_bbdev_log(ERR, "Failed to allocate %u vectors",
+ dev->data->num_queues);
+ return -ENOMEM;
}
ret = rte_intr_enable(dev->intr_handle);
desc->offset = desc_offset;
/* Set inbound data buffer address */
desc->in_addr_hi = (uint32_t)(
- rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
+ rte_pktmbuf_iova_offset(input, in_offset) >> 32);
desc->in_addr_lw = (uint32_t)(
- rte_pktmbuf_mtophys_offset(input, in_offset));
+ rte_pktmbuf_iova_offset(input, in_offset));
desc->out_addr_hi = (uint32_t)(
- rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
+ rte_pktmbuf_iova_offset(output, out_offset) >> 32);
desc->out_addr_lw = (uint32_t)(
- rte_pktmbuf_mtophys_offset(output, out_offset));
+ rte_pktmbuf_iova_offset(output, out_offset));
/* Save software context needed for dequeue */
desc->op_addr = op;
desc->done = 0;
/* Set inbound data buffer address */
desc->in_addr_hi = (uint32_t)(
- rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
+ rte_pktmbuf_iova_offset(input, in_offset) >> 32);
desc->in_addr_lw = (uint32_t)(
- rte_pktmbuf_mtophys_offset(input, in_offset));
+ rte_pktmbuf_iova_offset(input, in_offset));
desc->in_len = in_length;
desc->k = k;
desc->crc_type = !check_bit(op->turbo_dec.op_flags,
RTE_BBDEV_TURBO_CRC_TYPE_24B);
- if ((op->turbo_dec.code_block_mode == 0)
+ if ((op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
&& !check_bit(op->turbo_dec.op_flags,
RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP))
desc->drop_crc = 1;
desc->max_iter = op->turbo_dec.iter_max * 2;
desc->offset = desc_offset;
desc->out_addr_hi = (uint32_t)(
- rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
+ rte_pktmbuf_iova_offset(output, out_offset) >> 32);
desc->out_addr_lw = (uint32_t)(
- rte_pktmbuf_mtophys_offset(output, out_offset));
+ rte_pktmbuf_iova_offset(output, out_offset));
/* Save software context needed for dequeue */
desc->op_addr = op;
turbo_enc->rv_index);
return -1;
}
- if (turbo_enc->code_block_mode != 0 &&
- turbo_enc->code_block_mode != 1) {
+ if (turbo_enc->code_block_mode != RTE_BBDEV_TRANSPORT_BLOCK &&
+ turbo_enc->code_block_mode != RTE_BBDEV_CODE_BLOCK) {
rte_bbdev_log(ERR,
"code_block_mode (%u) is out of range 0 <= value <= 1",
turbo_enc->code_block_mode);
return -1;
}
- if (turbo_enc->code_block_mode == 0) {
+ if (turbo_enc->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) {
tb = &turbo_enc->tb_params;
if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE
|| tb->k_neg > RTE_BBDEV_TURBO_MAX_CB_SIZE)
turbo_dec->iter_min, turbo_dec->iter_max);
return -1;
}
- if (turbo_dec->code_block_mode != 0 &&
- turbo_dec->code_block_mode != 1) {
+ if (turbo_dec->code_block_mode != RTE_BBDEV_TRANSPORT_BLOCK &&
+ turbo_dec->code_block_mode != RTE_BBDEV_CODE_BLOCK) {
rte_bbdev_log(ERR,
"code_block_mode (%u) is out of range 0 <= value <= 1",
turbo_dec->code_block_mode);
return -1;
}
- if (turbo_dec->code_block_mode == 0) {
+ if (turbo_dec->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) {
if ((turbo_dec->op_flags &
RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP) &&
q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
for (i = 0; i < num; ++i) {
- if (ops[i]->turbo_enc.code_block_mode == 0) {
+ if (ops[i]->turbo_enc.code_block_mode ==
+ RTE_BBDEV_TRANSPORT_BLOCK) {
cbs_in_op = get_num_cbs_in_op_enc(&ops[i]->turbo_enc);
/* Check if there is available space for further
* processing
q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
for (i = 0; i < num; ++i) {
- if (ops[i]->turbo_dec.code_block_mode == 0) {
+ if (ops[i]->turbo_dec.code_block_mode ==
+ RTE_BBDEV_TRANSPORT_BLOCK) {
cbs_in_op = get_num_cbs_in_op_dec(&ops[i]->turbo_dec);
/* Check if there is available space for further
* processing
rte_bbdev_log_debug("DMA response desc %p", desc);
*op = desc->enc_req.op_addr;
- /* Check the decriptor error field, return 1 on error */
+ /* Check the descriptor error field, return 1 on error */
desc_error = check_desc_error(desc->enc_req.error);
(*op)->status = desc_error << RTE_BBDEV_DATA_ERROR;
for (cb_idx = 0; cb_idx < cbs_in_op; ++cb_idx) {
desc = q->ring_addr + ((q->head_free_desc + desc_offset +
cb_idx) & q->sw_ring_wrap_mask);
- /* Check the decriptor error field, return 1 on error */
+ /* Check the descriptor error field, return 1 on error */
desc_error = check_desc_error(desc->enc_req.error);
status |= desc_error << RTE_BBDEV_DATA_ERROR;
rte_bbdev_log_debug("DMA response desc %p", desc);
(*op)->turbo_dec.iter_count = (desc->dec_req.iter + 2) >> 1;
/* crc_pass = 0 when decoder fails */
(*op)->status = !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR;
- /* Check the decriptor error field, return 1 on error */
+ /* Check the descriptor error field, return 1 on error */
desc_error = check_desc_error(desc->enc_req.error);
(*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR;
return 1;
iter_count = RTE_MAX(iter_count, (uint8_t) desc->dec_req.iter);
/* crc_pass = 0 when decoder fails, one fails all */
status |= !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR;
- /* Check the decriptor error field, return 1 on error */
+ /* Check the descriptor error field, return 1 on error */
desc_error = check_desc_error(desc->enc_req.error);
status |= desc_error << RTE_BBDEV_DATA_ERROR;
rte_bbdev_log_debug("DMA response desc %p", desc);
for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
op = (q->ring_addr + ((q->head_free_desc + dequeued_cbs)
& q->sw_ring_wrap_mask))->enc_req.op_addr;
- if (op->turbo_enc.code_block_mode == 0)
+ if (op->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
ret = dequeue_enc_one_op_tb(q, &ops[i], dequeued_cbs);
else
ret = dequeue_enc_one_op_cb(q, &ops[i], dequeued_cbs);
for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
op = (q->ring_addr + ((q->head_free_desc + dequeued_cbs)
& q->sw_ring_wrap_mask))->dec_req.op_addr;
- if (op->turbo_dec.code_block_mode == 0)
+ if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs);
else
ret = dequeue_dec_one_op_cb(q, &ops[i], dequeued_cbs);
rte_bbdev_log_debug(
"Init device %s [%s] @ virtaddr %p phyaddr %#"PRIx64,
- dev->device->driver->name, dev->data->name,
+ drv->driver.name, dev->data->name,
(void *)pci_dev->mem_resource[0].addr,
pci_dev->mem_resource[0].phys_addr);
}
/* Fill HW specific part of device structure */
bbdev->device = &pci_dev->device;
- bbdev->intr_handle = &pci_dev->intr_handle;
+ bbdev->intr_handle = pci_dev->intr_handle;
bbdev->data->socket_id = pci_dev->device.numa_node;
/* Invoke FEC FPGA device initialization function */
((uint16_t)(version_id >> 16)), ((uint16_t)version_id));
#ifdef RTE_LIBRTE_BBDEV_DEBUG
- if (!strcmp(bbdev->device->driver->name,
+ if (!strcmp(pci_drv->driver.name,
RTE_STR(FPGA_LTE_FEC_PF_DRIVER_NAME)))
print_static_reg_debug_info(d->mmio_base);
#endif
}
static inline void
-set_default_fpga_conf(struct fpga_lte_fec_conf *def_conf)
+set_default_fpga_conf(struct rte_fpga_lte_fec_conf *def_conf)
{
/* clear default configuration before initialization */
- memset(def_conf, 0, sizeof(struct fpga_lte_fec_conf));
+ memset(def_conf, 0, sizeof(struct rte_fpga_lte_fec_conf));
/* Set pf mode to true */
def_conf->pf_mode_en = true;
/* Initial configuration of FPGA LTE FEC device */
int
-fpga_lte_fec_configure(const char *dev_name,
- const struct fpga_lte_fec_conf *conf)
+rte_fpga_lte_fec_configure(const char *dev_name,
+ const struct rte_fpga_lte_fec_conf *conf)
{
uint32_t payload_32, address;
uint16_t payload_16;
uint8_t payload_8;
uint16_t q_id, vf_id, total_q_id, total_ul_q_id, total_dl_q_id;
struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
- struct fpga_lte_fec_conf def_conf;
+ struct rte_fpga_lte_fec_conf def_conf;
if (bbdev == NULL) {
rte_bbdev_log(ERR,
RTE_PMD_REGISTER_PCI(FPGA_LTE_FEC_VF_DRIVER_NAME, fpga_lte_fec_pci_vf_driver);
RTE_PMD_REGISTER_PCI_TABLE(FPGA_LTE_FEC_VF_DRIVER_NAME,
pci_id_fpga_lte_fec_vf_map);
-
-RTE_INIT(fpga_lte_fec_init_log)
-{
- fpga_lte_fec_logtype = rte_log_register("pmd.bb.fpga_lte_fec");
- if (fpga_lte_fec_logtype >= 0)
-#ifdef RTE_LIBRTE_BBDEV_DEBUG
- rte_log_set_level(fpga_lte_fec_logtype, RTE_LOG_DEBUG);
-#else
- rte_log_set_level(fpga_lte_fec_logtype, RTE_LOG_NOTICE);
-#endif
-}