* It ensures that callback function assigned to that descriptor will
* invoked when any FPGA queue issues interrupt.
*/
- for (i = 0; i < FPGA_NUM_INTR_VEC; ++i)
- dev->intr_handle->efds[i] = dev->intr_handle->fd;
-
- if (!dev->intr_handle->intr_vec) {
- dev->intr_handle->intr_vec = rte_zmalloc("intr_vec",
- dev->data->num_queues * sizeof(int), 0);
- if (!dev->intr_handle->intr_vec) {
- rte_bbdev_log(ERR, "Failed to allocate %u vectors",
- dev->data->num_queues);
- return -ENOMEM;
- }
+ for (i = 0; i < FPGA_NUM_INTR_VEC; ++i) {
+ if (rte_intr_efds_index_set(dev->intr_handle, i,
+ rte_intr_fd_get(dev->intr_handle)))
+ return -rte_errno;
+ }
+
+ if (rte_intr_vec_list_alloc(dev->intr_handle, "intr_vec",
+ dev->data->num_queues)) {
+ rte_bbdev_log(ERR, "Failed to allocate %u vectors",
+ dev->data->num_queues);
+ return -ENOMEM;
}
ret = rte_intr_enable(dev->intr_handle);
rte_bbdev_log_debug("DMA response desc %p", desc);
*op = desc->enc_req.op_addr;
- /* Check the decriptor error field, return 1 on error */
+ /* Check the descriptor error field, return 1 on error */
desc_error = check_desc_error(desc->enc_req.error);
(*op)->status = desc_error << RTE_BBDEV_DATA_ERROR;
for (cb_idx = 0; cb_idx < cbs_in_op; ++cb_idx) {
desc = q->ring_addr + ((q->head_free_desc + desc_offset +
cb_idx) & q->sw_ring_wrap_mask);
- /* Check the decriptor error field, return 1 on error */
+ /* Check the descriptor error field, return 1 on error */
desc_error = check_desc_error(desc->enc_req.error);
status |= desc_error << RTE_BBDEV_DATA_ERROR;
rte_bbdev_log_debug("DMA response desc %p", desc);
(*op)->turbo_dec.iter_count = (desc->dec_req.iter + 2) >> 1;
/* crc_pass = 0 when decoder fails */
(*op)->status = !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR;
- /* Check the decriptor error field, return 1 on error */
+ /* Check the descriptor error field, return 1 on error */
desc_error = check_desc_error(desc->enc_req.error);
(*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR;
return 1;
iter_count = RTE_MAX(iter_count, (uint8_t) desc->dec_req.iter);
/* crc_pass = 0 when decoder fails, one fails all */
status |= !(desc->dec_req.crc_pass) << RTE_BBDEV_CRC_ERROR;
- /* Check the decriptor error field, return 1 on error */
+ /* Check the descriptor error field, return 1 on error */
desc_error = check_desc_error(desc->enc_req.error);
status |= desc_error << RTE_BBDEV_DATA_ERROR;
rte_bbdev_log_debug("DMA response desc %p", desc);
/* Fill HW specific part of device structure */
bbdev->device = &pci_dev->device;
- bbdev->intr_handle = &pci_dev->intr_handle;
+ bbdev->intr_handle = pci_dev->intr_handle;
bbdev->data->socket_id = pci_dev->device.numa_node;
/* Invoke FEC FPGA device initialization function */