};
/* FPGA LTE FEC DMA Encoding Request Descriptor */
-struct __attribute__((__packed__)) fpga_dma_enc_desc {
+struct __rte_packed fpga_dma_enc_desc {
uint32_t done:1,
rsrvd0:11,
error:4,
};
/* FPGA LTE FEC DMA Decoding Request Descriptor */
-struct __attribute__((__packed__)) fpga_dma_dec_desc {
+struct __rte_packed fpga_dma_dec_desc {
uint32_t done:1,
iter:5,
rsrvd0:2,
};
/* FPGA LTE FEC Ring Control Register */
-struct __attribute__((__packed__)) fpga_ring_ctrl_reg {
+struct __rte_packed fpga_ring_ctrl_reg {
uint64_t ring_base_addr;
uint64_t ring_head_addr;
uint16_t ring_size:11;
* completed. If completion flag is not updated within 1ms it is
* considered as a failure.
*/
- while (!(*((uint8_t *)d->flush_queue_status + q->q_idx) & payload)) {
+ while (!(*((volatile uint8_t *)d->flush_queue_status + q->q_idx) & payload)) {
if (counter > timeout) {
rte_bbdev_log(ERR, "FPGA Queue Flush failed for queue %d",
queue_id);