net/tap: set BPF syscall ID for RISC-V

[dpdk.git] / drivers / bus / dpaa / rte_dpaa_bus.h

diff --git a/drivers/bus/dpaa/rte_dpaa_bus.h b/drivers/bus/dpaa/rte_dpaa_bus.h
index 25aff2d..1f04d9e 100644 (file)
--- a/drivers/bus/dpaa/rte_dpaa_bus.h
+++ b/drivers/bus/dpaa/rte_dpaa_bus.h
@@ -1,12 +1,13 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- *   Copyright 2017-2019 NXP
+ *   Copyright 2017-2022 NXP
  *
  */
 #ifndef __RTE_DPAA_BUS_H__
 #define __RTE_DPAA_BUS_H__
 
 #include <rte_bus.h>
+#include <rte_mbuf_dyn.h>
 #include <rte_mempool.h>
 #include <dpaax_iova_table.h>
 
@@ -16,6 +17,34 @@
 #include <fsl_bman.h>
 #include <netcfg.h>
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* This sequence number field is used to store event entry index for
+ * driver specific usage. For parallel mode queues, invalid
+ * index will be set and for atomic mode queues, valid value
+ * ranging from 1 to 16.
+ */
+#define DPAA_INVALID_MBUF_SEQN  0
+
+typedef uint32_t dpaa_seqn_t;
+extern int dpaa_seqn_dynfield_offset;
+
+/**
+ * Read dpaa sequence number from mbuf.
+ *
+ * @param mbuf Structure to read from.
+ * @return pointer to dpaa sequence number.
+ */
+__rte_internal
+static inline dpaa_seqn_t *
+dpaa_seqn(struct rte_mbuf *mbuf)
+{
+       return RTE_MBUF_DYNFIELD(mbuf, dpaa_seqn_dynfield_offset,
+               dpaa_seqn_t *);
+}
+
 #define DPAA_MEMPOOL_OPS_NAME  "dpaa"
 
 #define DEV_TO_DPAA_DEVICE(ptr)        \
@@ -30,6 +59,12 @@
 #define SVR_LS1046A_FAMILY     0x87070000
 #define SVR_MASK               0xffff0000
 
+/** Device driver supports link state interrupt */
+#define RTE_DPAA_DRV_INTR_LSC  0x0008
+
+/** Number of supported QDMA devices */
+#define RTE_DPAA_QDMA_DEVICES  1
+
 #define RTE_DEV_TO_DPAA_CONST(ptr) \
        container_of(ptr, const struct rte_dpaa_device, device)
 
@@ -45,6 +80,7 @@ TAILQ_HEAD(rte_dpaa_driver_list, rte_dpaa_driver);
 enum rte_dpaa_type {
        FSL_DPAA_ETH = 1,
        FSL_DPAA_CRYPTO,
+       FSL_DPAA_QDMA
 };
 
 struct rte_dpaa_bus {
@@ -67,10 +103,11 @@ struct rte_dpaa_device {
        union {
                struct rte_eth_dev *eth_dev;
                struct rte_cryptodev *crypto_dev;
+               struct rte_dma_dev *dmadev;
        };
        struct rte_dpaa_driver *driver;
        struct dpaa_device_id id;
-       struct rte_intr_handle intr_handle;
+       struct rte_intr_handle *intr_handle;
        enum rte_dpaa_type device_type; /**< Ethernet or crypto type device */
        char name[RTE_ETH_NAME_MAX_LEN];
 };
@@ -86,6 +123,7 @@ struct rte_dpaa_driver {
        enum rte_dpaa_type drv_type;
        rte_dpaa_probe_t probe;
        rte_dpaa_remove_t remove;
+       uint32_t drv_flags;                 /**< Flags for controlling device.*/
 };
 
 /* Create storage for dqrr entries per lcore */
@@ -100,8 +138,6 @@ struct dpaa_portal {
        uint32_t bman_idx; /**< BMAN Portal ID*/
        uint32_t qman_idx; /**< QMAN Portal ID*/
        struct dpaa_portal_dqrr dpaa_held_bufs;
-       struct rte_crypto_op **dpaa_sec_ops;
-       int dpaa_sec_op_nb;
        uint64_t tid;/**< Parent Thread id for this portal */
 };
 
@@ -115,10 +151,6 @@ RTE_DECLARE_PER_LCORE(struct dpaa_portal *, dpaa_io);
        RTE_PER_LCORE(dpaa_io)->dpaa_held_bufs.dqrr_held
 #define DPAA_PER_LCORE_DQRR_MBUF(i) \
        RTE_PER_LCORE(dpaa_io)->dpaa_held_bufs.mbuf[i]
-#define DPAA_PER_LCORE_RTE_CRYPTO_OP \
-       RTE_PER_LCORE(dpaa_io)->dpaa_sec_ops
-#define DPAA_PER_LCORE_DPAA_SEC_OP_NB \
-       RTE_PER_LCORE(dpaa_io)->dpaa_sec_op_nb
 
 /* Various structures representing contiguous memory maps */
 struct dpaa_memseg {