net/dpaa2: change reference to private device

[dpdk.git] / drivers / bus / fslmc / portal / dpaa2_hw_pvt.h

diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index 678ee34..626fcbb 100644 (file)
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016 NXP
+ *   Copyright 2016-2018 NXP
  *
  */
 
@@ -32,11 +32,27 @@
 #define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
 #endif
 
-#define MAX_TX_RING_SLOTS      8
-       /** <Maximum number of slots available in TX ring*/
+/* Maximum number of slots available in TX ring */
+#define MAX_TX_RING_SLOTS                      32
 
-#define DPAA2_DQRR_RING_SIZE   16
-       /** <Maximum number of slots available in RX ring*/
+/* Maximum number of slots available in RX ring */
+#define DPAA2_EQCR_RING_SIZE           8
+/* Maximum number of slots available in RX ring on LX2 */
+#define DPAA2_LX2_EQCR_RING_SIZE       32
+
+/* Maximum number of slots available in RX ring */
+#define DPAA2_DQRR_RING_SIZE           16
+/* Maximum number of slots available in RX ring on LX2 */
+#define DPAA2_LX2_DQRR_RING_SIZE       32
+
+/* EQCR shift to get EQCR size (2 >> 3) = 8 for LS2/LS2 */
+#define DPAA2_EQCR_SHIFT               3
+/* EQCR shift to get EQCR size for LX2 (2 >> 5) = 32 for LX2 */
+#define DPAA2_LX2_EQCR_SHIFT           5
+
+#define DPAA2_SWP_CENA_REGION          0
+#define DPAA2_SWP_CINH_REGION          1
+#define DPAA2_SWP_CENA_MEM_REGION      2
 
 #define MC_PORTAL_INDEX                0
 #define NUM_DPIO_REGIONS       2
@@ -111,7 +127,10 @@ typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
 
 struct dpaa2_queue {
        struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
-       void *dev;
+       union {
+               struct rte_eth_dev_data *eth_data;
+               void *dev;
+       };
        int32_t eventfd;        /*!< Event Fd of this queue */
        uint32_t fqid;          /*!< Unique ID of this queue */
        uint8_t tc_index;       /*!< traffic class identifier */
@@ -125,6 +144,7 @@ struct dpaa2_queue {
        };
        struct rte_event ev;
        dpaa2_queue_cb_dqrr_t *cb;
+       struct dpaa2_bp_info *bp_array;
 };
 
 struct swp_active_dqs {
@@ -194,6 +214,12 @@ enum qbman_fd_format {
 #define DPAA2_RESET_FD_CTRL(fd)         ((fd)->simple.ctrl = 0)
 
 #define        DPAA2_SET_FD_ASAL(fd, asal)     ((fd)->simple.ctrl |= (asal << 16))
+
+#define DPAA2_RESET_FD_FLC(fd) do {    \
+       (fd)->simple.flc_lo = 0;        \
+       (fd)->simple.flc_hi = 0;        \
+} while (0)
+
 #define DPAA2_SET_FD_FLC(fd, addr)     do { \
        (fd)->simple.flc_lo = lower_32_bits((size_t)(addr));    \
        (fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr));  \