net/octeontx2: add security capabilities

[dpdk.git] / drivers / bus / fslmc / portal / dpaa2_hw_pvt.h

diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index 7f7e2fd..ab2b213 100644 (file)
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016-2018 NXP
+ *   Copyright 2016-2019 NXP
  *
  */
 
@@ -59,6 +59,8 @@
 #define DPAA2_SWP_CINH_REGION          1
 #define DPAA2_SWP_CENA_MEM_REGION      2
 
+#define DPAA2_MAX_TX_RETRY_COUNT       10000
+
 #define MC_PORTAL_INDEX                0
 #define NUM_DPIO_REGIONS       2
 #define NUM_DQS_PER_QUEUE       2
@@ -161,6 +163,8 @@ struct dpaa2_queue {
        dpaa2_queue_cb_dqrr_t *cb;
        dpaa2_queue_cb_eqresp_free_t *cb_eqresp_free;
        struct dpaa2_bp_info *bp_array;
+       /*to store tx_conf_queue corresponding to tx_queue*/
+       struct dpaa2_queue *tx_conf_queue;
 };
 
 struct swp_active_dqs {
@@ -183,6 +187,17 @@ struct dpaa2_dpci_dev {
        struct dpaa2_queue tx_queue[DPAA2_DPCI_MAX_QUEUES];
 };
 
+struct dpaa2_dpcon_dev {
+       TAILQ_ENTRY(dpaa2_dpcon_dev) next;
+       struct fsl_mc_io dpcon;
+       uint16_t token;
+       rte_atomic16_t in_use;
+       uint32_t dpcon_id;
+       uint16_t qbman_ch_id;
+       uint8_t num_priorities;
+       uint8_t channel_index;
+};
+
 /*! Global MCP list */
 extern void *(*rte_mcp_ptr_list);