bus/fslmc: register dpci as dpaa2 device for bus scan
[dpdk.git] / drivers / bus / fslmc / portal / dpaa2_hw_pvt.h
index f9f4e29..aee9592 100644 (file)
@@ -79,6 +79,8 @@
 #define DPAA2_HW_BUF_RESERVE   0
 #define DPAA2_PACKET_LAYOUT_ALIGN      64 /*changing from 256 */
 
+#define DPAA2_DPCI_MAX_QUEUES 2
+
 struct dpaa2_dpio_dev {
        TAILQ_ENTRY(dpaa2_dpio_dev) next;
                /**< Pointer to Next device instance */
@@ -142,6 +144,16 @@ struct swp_active_dqs {
 
 extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
 
+struct dpaa2_dpci_dev {
+       TAILQ_ENTRY(dpaa2_dpci_dev) next;
+               /**< Pointer to Next device instance */
+       struct fsl_mc_io dpci;  /** handle to DPCI portal object */
+       uint16_t token;
+       rte_atomic16_t in_use;
+       uint32_t dpci_id; /*HW ID for DPCI object */
+       struct dpaa2_queue queue[DPAA2_DPCI_MAX_QUEUES];
+};
+
 /*! Global MCP list */
 extern void *(*rte_mcp_ptr_list);
 
@@ -195,6 +207,13 @@ enum qbman_fd_format {
        fle->addr_lo = lower_32_bits((uint64_t)addr);     \
        fle->addr_hi = upper_32_bits((uint64_t)addr);     \
 } while (0)
+#define DPAA2_GET_FLE_CTXT(fle)                                        \
+       (uint64_t)((((uint64_t)((fle)->reserved[1])) << 32) + \
+                       (fle)->reserved[0])
+#define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
+       fle->reserved[0] = lower_32_bits((uint64_t)addr);     \
+       fle->reserved[1] = upper_32_bits((uint64_t)addr);         \
+} while (0)
 #define DPAA2_SET_FLE_OFFSET(fle, offset) \
        ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
 #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid)
@@ -336,4 +355,7 @@ void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
 
+struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
+void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);
+
 #endif