event/dpaa2: set priority as per DPCON device

[dpdk.git] / drivers / bus / fslmc / portal / dpaa2_hw_pvt.h

diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index 20c606d..db6dad5 100644 (file)
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -23,17 +23,13 @@
 #define lower_32_bits(x) ((uint32_t)(x))
 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
 
-#define SVR_LS1080A             0x87030000
-#define SVR_LS2080A             0x87010000
-#define SVR_LS2088A             0x87090000
-#define SVR_LX2160A             0x87360000
-
 #ifndef VLAN_TAG_SIZE
 #define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
 #endif
 
 /* Maximum number of slots available in TX ring */
 #define MAX_TX_RING_SLOTS                      32
+#define MAX_EQ_RESP_ENTRIES                    (MAX_TX_RING_SLOTS + 1)
 
 /* Maximum number of slots available in RX ring */
 #define DPAA2_EQCR_RING_SIZE           8
@@ -50,6 +46,15 @@
 /* EQCR shift to get EQCR size for LX2 (2 >> 5) = 32 for LX2 */
 #define DPAA2_LX2_EQCR_SHIFT           5
 
+/* Flag to determine an ordered queue mbuf */
+#define DPAA2_ENQUEUE_FLAG_ORP         (1ULL << 30)
+/* ORP ID shift and mask */
+#define DPAA2_EQCR_OPRID_SHIFT         16
+#define DPAA2_EQCR_OPRID_MASK          0x3FFF0000
+/* Sequence number shift and mask */
+#define DPAA2_EQCR_SEQNUM_SHIFT                0
+#define DPAA2_EQCR_SEQNUM_MASK         0x0000FFFF
+
 #define DPAA2_SWP_CENA_REGION          0
 #define DPAA2_SWP_CINH_REGION          1
 #define DPAA2_SWP_CENA_MEM_REGION      2
@@ -67,22 +72,29 @@
 #define DPAA2_MBUF_HW_ANNOTATION       64
 #define DPAA2_FD_PTA_SIZE              0
 
-#if (DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
-#error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
-#endif
-
 /* we will re-use the HEADROOM for annotation in RX */
 #define DPAA2_HW_BUF_RESERVE   0
 #define DPAA2_PACKET_LAYOUT_ALIGN      64 /*changing from 256 */
 
 #define DPAA2_DPCI_MAX_QUEUES 2
 
+struct dpaa2_queue;
+
+struct eqresp_metadata {
+       struct dpaa2_queue *dpaa2_q;
+       struct rte_mempool *mp;
+};
+
 struct dpaa2_dpio_dev {
        TAILQ_ENTRY(dpaa2_dpio_dev) next;
                /**< Pointer to Next device instance */
        uint16_t index; /**< Index of a instance in the list */
        rte_atomic16_t ref_count;
                /**< How many thread contexts are sharing this.*/
+       uint16_t eqresp_ci;
+       uint16_t eqresp_pi;
+       struct qbman_result *eqresp;
+       struct eqresp_metadata *eqresp_meta;
        struct fsl_mc_io *dpio; /** handle to DPIO portal object */
        uint16_t token;
        struct qbman_swp *sw_portal; /** SW portal object */
@@ -125,13 +137,18 @@ typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
                struct dpaa2_queue *rxq,
                struct rte_event *ev);
 
+typedef void (dpaa2_queue_cb_eqresp_free_t)(uint16_t eqresp_ci);
+
 struct dpaa2_queue {
        struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
-       void *dev;
-       int32_t eventfd;        /*!< Event Fd of this queue */
+       union {
+               struct rte_eth_dev_data *eth_data;
+               struct rte_cryptodev_data *crypto_data;
+       };
        uint32_t fqid;          /*!< Unique ID of this queue */
-       uint8_t tc_index;       /*!< traffic class identifier */
        uint16_t flow_id;       /*!< To be used by DPAA2 frmework */
+       uint8_t tc_index;       /*!< traffic class identifier */
+       uint8_t cgid;           /*! < Congestion Group id for this queue */
        uint64_t rx_pkts;
        uint64_t tx_pkts;
        uint64_t err_pkts;
@@ -140,8 +157,12 @@ struct dpaa2_queue {
                struct qbman_result *cscn;
        };
        struct rte_event ev;
+       int32_t eventfd;        /*!< Event Fd of this queue */
        dpaa2_queue_cb_dqrr_t *cb;
+       dpaa2_queue_cb_eqresp_free_t *cb_eqresp_free;
        struct dpaa2_bp_info *bp_array;
+       /*to store tx_conf_queue corresponding to tx_queue*/
+       struct dpaa2_queue *tx_conf_queue;
 };
 
 struct swp_active_dqs {
@@ -164,6 +185,17 @@ struct dpaa2_dpci_dev {
        struct dpaa2_queue tx_queue[DPAA2_DPCI_MAX_QUEUES];
 };
 
+struct dpaa2_dpcon_dev {
+       TAILQ_ENTRY(dpaa2_dpcon_dev) next;
+       struct fsl_mc_io dpcon;
+       uint16_t token;
+       rte_atomic16_t in_use;
+       uint32_t dpcon_id;
+       uint16_t qbman_ch_id;
+       uint8_t num_priorities;
+       uint8_t channel_index;
+};
+
 /*! Global MCP list */
 extern void *(*rte_mcp_ptr_list);
 
@@ -207,6 +239,7 @@ enum qbman_fd_format {
        ((fd)->simple.frc = (0x80000000 | (len)))
 #define DPAA2_GET_FD_FRC_PARSE_SUM(fd) \
                        ((uint16_t)(((fd)->simple.frc & 0xffff0000) >> 16))
+#define DPAA2_RESET_FD_FRC(fd)         ((fd)->simple.frc = 0)
 #define DPAA2_SET_FD_FRC(fd, _frc)     ((fd)->simple.frc = _frc)
 #define DPAA2_RESET_FD_CTRL(fd)         ((fd)->simple.ctrl = 0)