/****************/
/* arch assists */
/****************/
-#if defined(RTE_ARCH_ARM64)
+#if defined(RTE_ARCH_ARM)
+#if defined(RTE_ARCH_64)
#define dcbz(p) { asm volatile("dc zva, %0" : : "r" (p) : "memory"); }
#define lwsync() { asm volatile("dmb st" : : : "memory"); }
#define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
{
asm volatile("prfm pstl1keep, [%0, #0]" : : "r" (p));
}
-#elif defined(RTE_ARCH_ARM)
+#else /* RTE_ARCH_32 */
#define dcbz(p) memset(p, 0, 64)
#define lwsync() { asm volatile("dmb st" : : : "memory"); }
#define dcbf(p) RTE_SET_USED(p)
#define dccivac(p) RTE_SET_USED(p)
#define prefetch_for_load(p) { asm volatile ("pld [%0]" : : "r" (p)); }
#define prefetch_for_store(p) { asm volatile ("pld [%0]" : : "r" (p)); }
-
+#endif
#else
#define dcbz(p) RTE_SET_USED(p)
#define lwsync()