#include <rte_bus.h>
#include <rte_tailq.h>
#include <rte_devargs.h>
+#include <rte_mbuf.h>
+#include <rte_mbuf_dyn.h>
#include <fslmc_vfio.h>
#define FSLMC_OBJECT_MAX_LEN 32 /**< Length of each device on bus */
+#define DPAA2_INVALID_MBUF_SEQN 0
+
+typedef uint32_t dpaa2_seqn_t;
+extern int dpaa2_seqn_dynfield_offset;
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice
+ *
+ * Read dpaa2 sequence number from mbuf.
+ *
+ * @param mbuf Structure to read from.
+ * @return pointer to dpaa2 sequence number.
+ */
+__rte_experimental
+static inline dpaa2_seqn_t *
+dpaa2_seqn(struct rte_mbuf *mbuf)
+{
+ return RTE_MBUF_DYNFIELD(mbuf, dpaa2_seqn_dynfield_offset,
+ dpaa2_seqn_t *);
+}
/** Device driver supports link state interrupt */
#define RTE_DPAA2_DRV_INTR_LSC 0x0008
/**< Count of all devices scanned */
};
-#define DPAA2_PORTAL_DEQUEUE_DEPTH 32
-
-/* Create storage for dqrr entries per lcore */
-struct dpaa2_portal_dqrr {
- struct rte_mbuf *mbuf[DPAA2_PORTAL_DEQUEUE_DEPTH];
- uint64_t dqrr_held;
- uint8_t dqrr_size;
-};
-
-RTE_DECLARE_PER_LCORE(struct dpaa2_portal_dqrr, dpaa2_held_bufs);
-
-#define DPAA2_PER_LCORE_DQRR_SIZE \
- RTE_PER_LCORE(dpaa2_held_bufs).dqrr_size
-#define DPAA2_PER_LCORE_DQRR_HELD \
- RTE_PER_LCORE(dpaa2_held_bufs).dqrr_held
-#define DPAA2_PER_LCORE_DQRR_MBUF(i) \
- RTE_PER_LCORE(dpaa2_held_bufs).mbuf[i]
-
/**
* Register a DPAA2 driver.
*