dev->name, sizeof(dev->name));
devargs = pci_devargs_lookup(&dev->addr);
dev->device.devargs = devargs;
- /* In blacklist mode, if the device is not blacklisted, no
- * rte_devargs exists for it.
+
+ /* When using a blocklist, only blocked devices will have
+ * an rte_devargs. Allowed devices won't have one.
*/
if (devargs != NULL)
/* If an rte_devargs exists, the generic rte_device uses the
__func__, fd, requested_addr, size,
(unsigned long long)offset,
rte_strerror(rte_errno), mapaddr);
- mapaddr = MAP_FAILED; /* API uses mmap error code */
} else
RTE_LOG(DEBUG, EAL, " PCI memory mapped at %p\n", mapaddr);
loc = &dev->addr;
- /* The device is not blacklisted; Check if driver supports it */
+ /* The device is not blocked; Check if driver supports it */
if (!rte_pci_match(dr, dev))
/* Match of device and driver failed */
return 1;
loc->domain, loc->bus, loc->devid, loc->function,
dev->device.numa_node);
- /* no initialization when blacklisted, return without error */
+ /* no initialization when marked as blocked, return without error */
if (dev->device.devargs != NULL &&
- dev->device.devargs->policy ==
- RTE_DEV_BLACKLISTED) {
- RTE_LOG(INFO, EAL, " Device is blacklisted, not"
- " initializing\n");
+ dev->device.devargs->policy == RTE_DEV_BLOCKED) {
+ RTE_LOG(INFO, EAL, " Device is blocked, not initializing\n");
return 1;
}
struct rte_devargs *devargs = pci_devargs_lookup(pci_addr);
switch (rte_pci_bus.bus.conf.scan_mode) {
- case RTE_BUS_SCAN_WHITELIST:
- if (devargs && devargs->policy == RTE_DEV_WHITELISTED)
+ case RTE_BUS_SCAN_ALLOWLIST:
+ if (devargs && devargs->policy == RTE_DEV_ALLOWED)
return false;
break;
case RTE_BUS_SCAN_UNDEFINED:
- case RTE_BUS_SCAN_BLACKLIST:
- if (devargs == NULL ||
- devargs->policy != RTE_DEV_BLACKLISTED)
+ case RTE_BUS_SCAN_BLOCKLIST:
+ if (devargs == NULL || devargs->policy != RTE_DEV_BLOCKED)
return false;
break;
}
return iova_mode;
}
+off_t
+rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap)
+{
+ off_t offset = RTE_PCI_CFG_SPACE_SIZE;
+ uint32_t header;
+ int ttl;
+
+ /* minimum 8 bytes per capability */
+ ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
+
+ if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
+ RTE_LOG(ERR, EAL, "error in reading extended capabilities\n");
+ return -1;
+ }
+
+ /*
+ * If we have no capabilities, this is indicated by cap ID,
+ * cap version and next pointer all being 0.
+ */
+ if (header == 0)
+ return 0;
+
+ while (ttl != 0) {
+ if (RTE_PCI_EXT_CAP_ID(header) == cap)
+ return offset;
+
+ offset = RTE_PCI_EXT_CAP_NEXT(header);
+
+ if (offset < RTE_PCI_CFG_SPACE_SIZE)
+ break;
+
+ if (rte_pci_read_config(dev, &header, 4, offset) < 0) {
+ RTE_LOG(ERR, EAL,
+ "error in reading extended capabilities\n");
+ return -1;
+ }
+
+ ttl--;
+ }
+
+ return 0;
+}
+
struct rte_pci_bus rte_pci_bus = {
.bus = {
.scan = rte_pci_scan,