plt_free(irq_chip);
}
-void
+static void
roc_bphy_irq_stack_remove(int cpu)
{
struct roc_bphy_irq_stack *curr_stack;
pthread_mutex_unlock(&stacks_mutex);
}
-void *
+static void *
roc_bphy_irq_stack_get(int cpu)
{
#define ARM_STACK_ALIGNMENT (2 * sizeof(void *))
roc_atf_ret();
}
-int
+static int
roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
void (*isr)(int irq_num, void *isr_data),
void *isr_data)
CPU_ZERO(&intr_cpuset);
CPU_SET(curr_cpu, &intr_cpuset);
- retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+ rc = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
&intr_cpuset);
if (rc < 0) {
plt_err("Failed to set affinity mask");
return irq_chip->avail_irq_bmask & BIT(irq_num);
}
+uint64_t
+roc_bphy_intr_max_get(struct roc_bphy_irq_chip *irq_chip)
+{
+ return irq_chip->max_irq;
+}
+
int
-roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num)
+roc_bphy_intr_clear(struct roc_bphy_irq_chip *chip, int irq_num)
{
roc_cpuset_t orig_cpuset, intr_cpuset;
const struct plt_memzone *mz;