/* Clear interrupt */
plt_write64(intr, nix->base + NIX_LF_ERR_INT);
+ /* Dump registers to std out */
+ roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
+ roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix));
}
static int
nix_lf_register_err_irq(struct nix *nix)
{
- struct plt_intr_handle *handle = &nix->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
int rc, vec;
vec = nix->msixoff + NIX_LF_INT_VEC_ERR_INT;
static void
nix_lf_unregister_err_irq(struct nix *nix)
{
- struct plt_intr_handle *handle = &nix->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
int vec;
vec = nix->msixoff + NIX_LF_INT_VEC_ERR_INT;
plt_err("Ras_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
/* Clear interrupt */
plt_write64(intr, nix->base + NIX_LF_RAS);
+
+ /* Dump registers to std out */
+ roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
+ roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix));
}
static int
nix_lf_register_ras_irq(struct nix *nix)
{
- struct plt_intr_handle *handle = &nix->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
int rc, vec;
vec = nix->msixoff + NIX_LF_INT_VEC_POISON;
static void
nix_lf_unregister_ras_irq(struct nix *nix)
{
- struct plt_intr_handle *handle = &nix->pci_dev->intr_handle;
+ struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
int vec;
vec = nix->msixoff + NIX_LF_INT_VEC_POISON;
return nix_lf_q_irq_get_and_clear(nix, sq, NIX_LF_SQ_OP_INT, ~0x1ff00);
}
-static inline void
+static inline bool
+nix_lf_is_sqb_null(struct dev *dev, int q)
+{
+ bool is_sqb_null = false;
+ volatile void *ctx;
+ int rc;
+
+ rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, q, &ctx);
+ if (rc) {
+ plt_err("Failed to get sq context");
+ } else {
+ is_sqb_null =
+ roc_model_is_cn9k() ?
+ (((__io struct nix_sq_ctx_s *)ctx)->next_sqb ==
+ 0) :
+ (((__io struct nix_cn10k_sq_ctx_s *)ctx)
+ ->next_sqb == 0);
+ }
+
+ return is_sqb_null;
+}
+
+static inline uint8_t
nix_lf_sq_debug_reg(struct nix *nix, uint32_t off)
{
+ uint8_t err = 0;
uint64_t reg;
reg = plt_read64(nix->base + off);
- if (reg & BIT_ULL(44))
- plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff),
- (uint8_t)(reg & 0xff));
+ if (reg & BIT_ULL(44)) {
+ err = reg & 0xff;
+ /* Clear valid bit */
+ plt_write64(BIT_ULL(44), nix->base + off);
+ }
+
+ return err;
}
static void
struct dev *dev = &nix->dev;
int q, cq, rq, sq;
uint64_t intr;
+ uint8_t rc;
intr = plt_read64(nix->base + NIX_LF_QINTX_INT(qintx));
if (intr == 0)
sq = q % nix->qints;
irq = nix_lf_sq_irq_get_and_clear(nix, sq);
- if (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) {
- plt_err("SQ=%d NIX_SQINT_LMT_ERR", sq);
- nix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG);
- }
- if (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
- plt_err("SQ=%d NIX_SQINT_MNQ_ERR", sq);
- nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG);
- }
- if (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) {
- plt_err("SQ=%d NIX_SQINT_SEND_ERR", sq);
- nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG);
- }
- if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) {
+ /* Detect LMT store error */
+ rc = nix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG);
+ if (rc)
+ plt_err("SQ=%d NIX_SQINT_LMT_ERR, errcode %x", sq, rc);
+
+ /* Detect Meta-descriptor enqueue error */
+ rc = nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG);
+ if (rc)
+ plt_err("SQ=%d NIX_SQINT_MNQ_ERR, errcode %x", sq, rc);
+
+ /* Detect Send error */
+ rc = nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG);
+ if (rc)
+ plt_err("SQ=%d NIX_SQINT_SEND_ERR, errcode %x", sq, rc);
+
+ /* Detect SQB fault, read SQ context to check SQB NULL case */
+ if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL) ||
+ nix_lf_is_sqb_null(dev, q))
plt_err("SQ=%d NIX_SQINT_SQB_ALLOC_FAIL", sq);
- nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG);
- }
}
/* Clear interrupt */
plt_write64(intr, nix->base + NIX_LF_QINTX_INT(qintx));
+
+ /* Dump registers to std out */
+ roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
+ roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix));
}
int
struct nix *nix;
nix = roc_nix_to_nix_priv(roc_nix);
- handle = &nix->pci_dev->intr_handle;
+ handle = nix->pci_dev->intr_handle;
/* Figure out max qintx required */
rqs = PLT_MIN(nix->qints, nix->nb_rx_queues);
int vec, q;
nix = roc_nix_to_nix_priv(roc_nix);
- handle = &nix->pci_dev->intr_handle;
+ handle = nix->pci_dev->intr_handle;
for (q = 0; q < nix->configured_qints; q++) {
vec = nix->msixoff + NIX_LF_INT_VEC_QINT_START + q;
struct nix *nix;
nix = roc_nix_to_nix_priv(roc_nix);
- handle = &nix->pci_dev->intr_handle;
+ handle = nix->pci_dev->intr_handle;
nix->configured_cints = PLT_MIN(nix->cints, nix->nb_rx_queues);
return rc;
}
- if (!handle->intr_vec) {
- handle->intr_vec = plt_zmalloc(
- nix->configured_cints * sizeof(int), 0);
- if (!handle->intr_vec) {
- plt_err("Failed to allocate %d rx intr_vec",
- nix->configured_cints);
- return -ENOMEM;
- }
+ rc = plt_intr_vec_list_alloc(handle, "cnxk",
+ nix->configured_cints);
+ if (rc) {
+ plt_err("Fail to allocate intr vec list, rc=%d",
+ rc);
+ return rc;
}
- /* VFIO vector zero is resereved for misc interrupt so
+ /* VFIO vector zero is reserved for misc interrupt so
* doing required adjustment. (b13bfab4cd)
*/
- handle->intr_vec[q] = PLT_INTR_VEC_RXTX_OFFSET + vec;
+ if (plt_intr_vec_list_index_set(handle, q,
+ PLT_INTR_VEC_RXTX_OFFSET + vec))
+ return -1;
/* Configure CQE interrupt coalescing parameters */
plt_write64(((CQ_CQE_THRESH_DEFAULT) |
int vec, q;
nix = roc_nix_to_nix_priv(roc_nix);
- handle = &nix->pci_dev->intr_handle;
+ handle = nix->pci_dev->intr_handle;
for (q = 0; q < nix->configured_cints; q++) {
vec = nix->msixoff + NIX_LF_INT_VEC_CINT_START + q;
dev_irq_unregister(handle, nix_lf_cq_irq, &nix->cints_mem[q],
vec);
}
+
+ plt_intr_vec_list_free(handle);
plt_free(nix->cints_mem);
}