aq->rq.rq_int_ena = 0;
/* Many to one reduction */
aq->rq.qint_idx = rq->qid % qints;
- aq->rq.xqe_drop_ena = 1;
+ aq->rq.xqe_drop_ena = 0;
+ aq->rq.lpb_drop_ena = rq->lpb_drop_ena;
+ aq->rq.spb_drop_ena = rq->spb_drop_ena;
/* If RED enabled, then fill enable for all cases */
if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
aq->rq_mask.rq_int_ena = ~aq->rq_mask.rq_int_ena;
aq->rq_mask.qint_idx = ~aq->rq_mask.qint_idx;
aq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;
+ aq->rq_mask.lpb_drop_ena = ~aq->rq_mask.lpb_drop_ena;
+ aq->rq_mask.spb_drop_ena = ~aq->rq_mask.spb_drop_ena;
if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
aq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;
/* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
cq_ctx->cint_idx = cq->qid;
- if (roc_model_is_cn96_a0() || roc_model_is_cn95_a0()) {
+ if (roc_errata_nix_has_cq_min_size_4k()) {
const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
uint16_t min_rx_drop;
memset(&aura, 0, sizeof(aura));
aura.fc_ena = 1;
- if (roc_model_is_cn9k() || roc_model_is_cn10ka_a0())
+ if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp())
aura.fc_stype = 0x0; /* STF */
else
aura.fc_stype = 0x3; /* STSTP */
sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,
uint16_t smq)
{
+ struct roc_nix *roc_nix = nix_priv_to_roc_nix(nix);
struct mbox *mbox = (&nix->dev)->mbox;
struct nix_aq_enq_req *aq;
aq->sq.max_sqe_size = sq->max_sqe_sz;
aq->sq.smq = smq;
aq->sq.smq_rr_quantum = rr_quantum;
- aq->sq.default_chan = nix->tx_chan_base;
+ if (roc_nix_is_sdp(roc_nix))
+ aq->sq.default_chan =
+ nix->tx_chan_base + (sq->qid % nix->tx_chan_cnt);
+ else
+ aq->sq.default_chan = nix->tx_chan_base;
aq->sq.sqe_stype = NIX_STYPE_STF;
aq->sq.ena = 1;
aq->sq.sso_ena = !!sq->sso_ena;