common/mlx5: use new port query API if available

[dpdk.git] / drivers / common / mlx5 / mlx5_common.h

diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h
index bc200e2..306f2f1 100644 (file)
--- a/drivers/common/mlx5/mlx5_common.h
+++ b/drivers/common/mlx5/mlx5_common.h
@@ -8,23 +8,20 @@
 #include <stdio.h>
 
 #include <rte_pci.h>
+#include <rte_debug.h>
 #include <rte_atomic.h>
 #include <rte_log.h>
 #include <rte_kvargs.h>
 #include <rte_devargs.h>
+#include <rte_bitops.h>
+#include <rte_os_shim.h>
 
 #include "mlx5_prm.h"
+#include "mlx5_devx_cmds.h"
+#include "mlx5_common_os.h"
 
-
-/*
- * Compilation workaround for PPC64 when AltiVec is fully enabled, e.g. std=c11.
- * Otherwise there would be a type conflict between stdbool and altivec.
- */
-#if defined(__PPC64__) && !defined(__APPLE_ALTIVEC__)
-#undef bool
-/* redefine as in stdbool.h */
-#define bool _Bool
-#endif
+/* Reported driver name. */
+#define MLX5_PCI_DRIVER_NAME "mlx5_pci"
 
 /* Bit-field manipulation. */
 #define BITFIELD_DECLARE(bf, type, size) \
@@ -70,10 +67,6 @@ pmd_drv_log_basename(const char *s)
                        RTE_FMT_HEAD(__VA_ARGS__,), \
                RTE_FMT_TAIL(__VA_ARGS__,)))
 
-/*
- * When debugging is enabled (MLX5_DEBUG not defined), file, line and function
- * information replace the driver name (MLX5_DRIVER_NAME) in log messages.
- */
 #ifdef RTE_LIBRTE_MLX5_DEBUG
 
 #define PMD_DRV_LOG__(level, type, name, ...) \
@@ -97,14 +90,12 @@ pmd_drv_log_basename(const char *s)
 /* claim_zero() does not perform any check when debugging is disabled. */
 #ifdef RTE_LIBRTE_MLX5_DEBUG
 
-#define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__)
 #define MLX5_ASSERT(exp) RTE_VERIFY(exp)
 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0)
 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0)
 
 #else /* RTE_LIBRTE_MLX5_DEBUG */
 
-#define DEBUG(...) (void)0
 #define MLX5_ASSERT(exp) RTE_ASSERT(exp)
 #define claim_zero(...) (__VA_ARGS__)
 #define claim_nonzero(...) (__VA_ARGS__)
@@ -136,7 +127,11 @@ enum {
        PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
        PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
        PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
-       PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
+       PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e,
+       PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6,
+       PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f,
+       PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021,
+       PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc,
 };
 
 /* Maximum number of simultaneous unicast MAC addresses. */
@@ -153,6 +148,8 @@ enum mlx5_nl_phys_port_name_type {
        MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
        MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
        MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
+       MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */
+       MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */
        MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
 };
 
@@ -161,6 +158,7 @@ struct mlx5_switch_info {
        uint32_t master:1; /**< Master device. */
        uint32_t representor:1; /**< Representor device. */
        enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */
+       int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */
        int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
        int32_t port_name; /**< Representor port name. */
        uint64_t switch_id; /**< Switch identifier. */
@@ -197,25 +195,51 @@ check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
 
        if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
                return MLX5_CQE_STATUS_HW_OWN;
-       rte_cio_rmb();
+       rte_io_rmb();
        if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
                     op_code == MLX5_CQE_REQ_ERR))
                return MLX5_CQE_STATUS_ERR;
        return MLX5_CQE_STATUS_SW_OWN;
 }
 
+__rte_internal
 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
+__rte_internal
+int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname);
 
-#define MLX5_CLASS_ARG_NAME "class"
 
 enum mlx5_class {
-       MLX5_CLASS_NET,
-       MLX5_CLASS_VDPA,
        MLX5_CLASS_INVALID,
+       MLX5_CLASS_NET = RTE_BIT64(0),
+       MLX5_CLASS_VDPA = RTE_BIT64(1),
+       MLX5_CLASS_REGEX = RTE_BIT64(2),
+       MLX5_CLASS_COMPRESS = RTE_BIT64(3),
 };
 
-enum mlx5_class mlx5_class_get(struct rte_devargs *devargs);
+#define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
+
+/* devX creation object */
+struct mlx5_devx_obj {
+       void *obj; /* The DV object. */
+       int id; /* The object ID. */
+};
+
+/* UMR memory buffer used to define 1 entry in indirect mkey. */
+struct mlx5_klm {
+       uint32_t byte_count;
+       uint32_t mkey;
+       uint64_t address;
+};
+
+__rte_internal
 void mlx5_translate_port_name(const char *port_name_in,
                              struct mlx5_switch_info *port_info_out);
+void mlx5_glue_constructor(void);
+__rte_internal
+void *mlx5_devx_alloc_uar(void *ctx, int mapping);
+extern uint8_t haswell_broadwell_cpu;
+
+__rte_internal
+void mlx5_common_init(void);
 
 #endif /* RTE_PMD_MLX5_COMMON_H_ */