#include "mlx5_prm.h"
#include "mlx5_devx_cmds.h"
+/* Reported driver name. */
+#define MLX5_DRIVER_NAME "mlx5_pci"
/* Bit-field manipulation. */
#define BITFIELD_DECLARE(bf, type, size) \
PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
- PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
+ PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e,
PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6,
PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f,
+ PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021,
+ PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc,
};
/* Maximum number of simultaneous unicast MAC addresses. */
if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
return MLX5_CQE_STATUS_HW_OWN;
- rte_cio_rmb();
+ rte_io_rmb();
if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
op_code == MLX5_CQE_REQ_ERR))
return MLX5_CQE_STATUS_ERR;
MLX5_CLASS_REGEX = RTE_BIT64(2),
};
-#define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
-#define MLX5_DBR_SIZE 8
-#define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
-#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
+#define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
+#define MLX5_DBR_PER_PAGE 64
+/* Must be >= CHAR_BIT * sizeof(uint64_t) */
+#define MLX5_DBR_PAGE_SIZE (MLX5_DBR_PER_PAGE * MLX5_DBR_SIZE)
+/* Page size must be >= 512. */
+#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / (CHAR_BIT * sizeof(uint64_t)))
struct mlx5_devx_dbr_page {
/* Door-bell records, must be first member in structure. */
LIST_HEAD(mlx5_dbr_page_list, mlx5_devx_dbr_page);
-__rte_internal
-enum mlx5_class mlx5_class_get(struct rte_devargs *devargs);
__rte_internal
void mlx5_translate_port_name(const char *port_name_in,
struct mlx5_switch_info *port_info_out);
__rte_internal
int32_t mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id,
uint64_t offset);
+__rte_internal
+void *mlx5_devx_alloc_uar(void *ctx, int mapping);
extern uint8_t haswell_broadwell_cpu;
__rte_internal