raw/ifpga: add APIs to get FPGA information

[dpdk.git] / drivers / common / mlx5 / mlx5_devx_cmds.c

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index b075af9..0060c37 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -53,8 +53,8 @@ mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
        MLX5_SET(access_register_in, in, register_id, reg_id);
        MLX5_SET(access_register_in, in, argument, arg);
        rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
-                                        MLX5_ST_SZ_DW(access_register_out) *
-                                        sizeof(uint32_t) + dw_cnt);
+                                        MLX5_ST_SZ_BYTES(access_register_out) +
+                                        sizeof(uint32_t) * dw_cnt);
        if (rc)
                goto error;
        status = MLX5_GET(access_register_out, out, status);
@@ -744,6 +744,11 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
                                              log_compress_mmo_size);
        attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
                                                log_decompress_mmo_size);
+       attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
+       attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
+                                               mini_cqe_resp_flow_tag);
+       attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
+                                                mini_cqe_resp_l3_l4_tag);
        if (attr->qos.sup) {
                MLX5_SET(query_hca_cap_in, in, op_mod,
                         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
@@ -2160,3 +2165,103 @@ mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
        return geneve_tlv_opt_obj;
 }
 
+int
+mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
+{
+#ifdef HAVE_IBV_FLOW_DV_SUPPORT
+       uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
+       uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
+       int rc;
+       void *rq_ctx;
+
+       MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
+       MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
+       rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
+       if (rc) {
+               rte_errno = errno;
+               DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
+                       "rc = %d, errno = %d.", rc, errno);
+               return -rc;
+       };
+       rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
+       *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
+       return 0;
+#else
+       (void)wq;
+       (void)counter_set_id;
+       return -ENOTSUP;
+#endif
+}
+
+/*
+ * Allocate queue counters via devx interface.
+ *
+ * @param[in] ctx
+ *   Context returned from mlx5 open_device() glue function.
+ *
+ * @return
+ *   Pointer to counter object on success, a NULL value otherwise and
+ *   rte_errno is set.
+ */
+struct mlx5_devx_obj *
+mlx5_devx_cmd_queue_counter_alloc(void *ctx)
+{
+       struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
+                                               SOCKET_ID_ANY);
+       uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
+       uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
+
+       if (!dcs) {
+               rte_errno = ENOMEM;
+               return NULL;
+       }
+       MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
+       dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
+                                             sizeof(out));
+       if (!dcs->obj) {
+               DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
+                       "%d.", errno);
+               rte_errno = errno;
+               mlx5_free(dcs);
+               return NULL;
+       }
+       dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
+       return dcs;
+}
+
+/**
+ * Query queue counters values.
+ *
+ * @param[in] dcs
+ *   devx object of the queue counter set.
+ * @param[in] clear
+ *   Whether hardware should clear the counters after the query or not.
+ *  @param[out] out_of_buffers
+ *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
+ *
+ * @return
+ *   0 on success, a negative value otherwise.
+ */
+int
+mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
+                                 uint32_t *out_of_buffers)
+{
+       uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
+       uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
+       int rc;
+
+       MLX5_SET(query_q_counter_in, in, opcode,
+                MLX5_CMD_OP_QUERY_Q_COUNTER);
+       MLX5_SET(query_q_counter_in, in, op_mod, 0);
+       MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
+       MLX5_SET(query_q_counter_in, in, clear, !!clear);
+       rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
+                                      sizeof(out));
+       if (rc) {
+               DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
+               rte_errno = rc;
+               return -rc;
+       }
+       *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
+       return 0;
+}