relaxed_ordering_write);
attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
relaxed_ordering_read);
+ attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
+ access_register_user);
attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
eth_net_offloads);
attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
if (!attr->eth_net_offloads)
return 0;
+ /* Query Flow Sampler Capability From FLow Table Properties Layout. */
+ memset(in, 0, sizeof(in));
+ memset(out, 0, sizeof(out));
+ MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
+ MLX5_SET(query_hca_cap_in, in, op_mod,
+ MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+
+ rc = mlx5_glue->devx_general_cmd(ctx,
+ in, sizeof(in),
+ out, sizeof(out));
+ if (rc)
+ goto error;
+ status = MLX5_GET(query_hca_cap_out, out, status);
+ syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
+ if (status) {
+ DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
+ "status %x, syndrome = %x",
+ status, syndrome);
+ attr->log_max_ft_sampler_num = 0;
+ return -1;
+ }
+ hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
+ attr->log_max_ft_sampler_num =
+ MLX5_GET(flow_table_nic_cap,
+ hcattr, flow_table_properties.log_max_ft_sampler_num);
+
/* Query HCA offloads for Ethernet protocol. */
memset(in, 0, sizeof(in));
memset(out, 0, sizeof(out));
MLX5_GET(per_protocol_networking_offload_caps, hcattr,
lro_timer_supported_periods[i]);
}
+ attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, lro_min_mss_size);
attr->tunnel_stateless_geneve_rx =
MLX5_GET(per_protocol_networking_offload_caps,
hcattr, tunnel_stateless_geneve_rx);
return tir;
}
+/**
+ * Modify TIR using DevX API.
+ *
+ * @param[in] tir
+ * Pointer to TIR DevX object structure.
+ * @param [in] modify_tir_attr
+ * Pointer to TIR modification attributes structure.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
+ struct mlx5_devx_modify_tir_attr *modify_tir_attr)
+{
+ struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
+ uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
+ uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
+ void *tir_ctx;
+ int ret;
+
+ MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
+ MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
+ MLX5_SET64(modify_tir_in, in, modify_bitmask,
+ modify_tir_attr->modify_bitmask);
+ tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
+ if (modify_tir_attr->modify_bitmask &
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
+ MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
+ tir_attr->lro_timeout_period_usecs);
+ MLX5_SET(tirc, tir_ctx, lro_enable_mask,
+ tir_attr->lro_enable_mask);
+ MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
+ tir_attr->lro_max_msg_sz);
+ }
+ if (modify_tir_attr->modify_bitmask &
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
+ MLX5_SET(tirc, tir_ctx, indirect_table,
+ tir_attr->indirect_table);
+ if (modify_tir_attr->modify_bitmask &
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
+ int i;
+ void *outer, *inner;
+
+ MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
+ tir_attr->rx_hash_symmetric);
+ MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
+ for (i = 0; i < 10; i++) {
+ MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
+ tir_attr->rx_hash_toeplitz_key[i]);
+ }
+ outer = MLX5_ADDR_OF(tirc, tir_ctx,
+ rx_hash_field_selector_outer);
+ MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
+ tir_attr->rx_hash_field_selector_outer.l3_prot_type);
+ MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
+ tir_attr->rx_hash_field_selector_outer.l4_prot_type);
+ MLX5_SET
+ (rx_hash_field_select, outer, selected_fields,
+ tir_attr->rx_hash_field_selector_outer.selected_fields);
+ inner = MLX5_ADDR_OF(tirc, tir_ctx,
+ rx_hash_field_selector_inner);
+ MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
+ tir_attr->rx_hash_field_selector_inner.l3_prot_type);
+ MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
+ tir_attr->rx_hash_field_selector_inner.l4_prot_type);
+ MLX5_SET
+ (rx_hash_field_select, inner, selected_fields,
+ tir_attr->rx_hash_field_selector_inner.selected_fields);
+ }
+ if (modify_tir_attr->modify_bitmask &
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
+ MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
+ }
+ ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
+ out, sizeof(out));
+ if (ret) {
+ DRV_LOG(ERR, "Failed to modify TIR using DevX");
+ rte_errno = errno;
+ return -errno;
+ }
+ return ret;
+}
+
/**
* Create RQT using DevX API.
*
MLX5_ADAPTER_PAGE_SHIFT);
MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
+ MLX5_SET(cqc, cqctx, cqe_comp_en, attr->cqe_comp_en);
+ MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
+ MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
if (attr->q_umem_valid) {
MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);