#include "mlx5_common_log.h"
#include "mlx5_malloc.h"
+static void *
+mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
+ int *err, uint32_t flags)
+{
+ const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
+ const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
+ int status, syndrome, rc;
+
+ if (err)
+ *err = 0;
+ memset(in, 0, size_in);
+ memset(out, 0, size_out);
+ MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
+ MLX5_SET(query_hca_cap_in, in, op_mod, flags);
+ rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
+ if (rc) {
+ DRV_LOG(ERR,
+ "Failed to query devx HCA capabilities func %#02x",
+ flags >> 1);
+ if (err)
+ *err = rc > 0 ? -rc : rc;
+ return NULL;
+ }
+ status = MLX5_GET(query_hca_cap_out, out, status);
+ syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
+ if (status) {
+ DRV_LOG(ERR,
+ "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x",
+ flags >> 1, status, syndrome);
+ if (err)
+ *err = -1;
+ return NULL;
+ }
+ return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
+}
+
/**
* Perform read access to the registers. Reads data from register
* and writes ones to the specified buffer.
mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
struct mlx5_hca_vdpa_attr *vdpa_attr)
{
- uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
- uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
- void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
- int status, syndrome, rc;
+ uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
+ uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
+ void *hcattr;
- MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
- MLX5_SET(query_hca_cap_in, in, op_mod,
- MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
- MLX5_HCA_CAP_OPMOD_GET_CUR);
- rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
- status = MLX5_GET(query_hca_cap_out, out, status);
- syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
- if (rc || status) {
- RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
- " status %x, syndrome = %x", status, syndrome);
+ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
+ MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ if (!hcattr) {
+ RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities");
vdpa_attr->valid = 0;
} else {
vdpa_attr->valid = 1;
return parse_flex_obj;
}
+static int
+mlx5_devx_cmd_query_hca_parse_graph_node_cap
+ (void *ctx, struct mlx5_hca_flex_attr *attr)
+{
+ uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
+ uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
+ void *hcattr;
+ int rc;
+
+ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
+ MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ if (!hcattr)
+ return rc;
+ attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
+ attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
+ attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
+ header_length_mode);
+ attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
+ sample_offset_mode);
+ attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
+ max_num_arc_in);
+ attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
+ max_num_arc_out);
+ attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
+ max_num_sample);
+ attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
+ sample_id_in_out);
+ attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
+ max_base_header_length);
+ attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
+ max_sample_base_offset);
+ attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
+ max_next_header_offset);
+ attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
+ header_length_mask_width);
+ /* Get the max supported samples from HCA CAP 2 */
+ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
+ MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ if (!hcattr)
+ return rc;
+ attr->max_num_prog_sample =
+ MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
+ return 0;
+}
+
static int
mlx5_devx_query_pkt_integrity_match(void *hcattr)
{
{
uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
- void *hcattr;
- int status, syndrome, rc, i;
uint64_t general_obj_types_supported = 0;
+ void *hcattr;
+ int rc, i;
- MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
- MLX5_SET(query_hca_cap_in, in, op_mod,
- MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
- MLX5_HCA_CAP_OPMOD_GET_CUR);
-
- rc = mlx5_glue->devx_general_cmd(ctx,
- in, sizeof(in), out, sizeof(out));
- if (rc)
- goto error;
- status = MLX5_GET(query_hca_cap_out, out, status);
- syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
- if (status) {
- DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
- "status %x, syndrome = %x", status, syndrome);
- return -1;
- }
- hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
+ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
+ MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ if (!hcattr)
+ return rc;
attr->flow_counter_bulk_alloc_bitmap =
MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
attr->steering_format_version =
MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
- attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
+ attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
+ attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
regexp_num_of_engines);
/* Read the general_obj_types bitmap and extract the relevant bits. */
general_obj_types) &
MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
if (attr->qos.sup) {
- MLX5_SET(query_hca_cap_in, in, op_mod,
- MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
- MLX5_HCA_CAP_OPMOD_GET_CUR);
- rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
- out, sizeof(out));
- if (rc)
- goto error;
- if (status) {
- DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
- " status %x, syndrome = %x", status, syndrome);
- return -1;
+ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
+ MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ if (!hcattr) {
+ DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
+ return rc;
}
- hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
attr->qos.flow_meter_old =
MLX5_GET(qos_cap, hcattr, flow_meter_old);
attr->qos.log_max_flow_meter =
log_max_num_meter_aso);
}
}
+ /*
+ * Flex item support needs max_num_prog_sample_field
+ * from the Capabilities 2 table for PARSE_GRAPH_NODE
+ */
+ if (attr->parse_graph_flex_node) {
+ rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
+ (ctx, &attr->flex);
+ if (rc)
+ return -1;
+ }
if (attr->vdpa.valid)
mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
if (!attr->eth_net_offloads)
return 0;
-
/* Query Flow Sampler Capability From FLow Table Properties Layout. */
- memset(in, 0, sizeof(in));
- memset(out, 0, sizeof(out));
- MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
- MLX5_SET(query_hca_cap_in, in, op_mod,
- MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
- MLX5_HCA_CAP_OPMOD_GET_CUR);
-
- rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
- if (rc)
- goto error;
- status = MLX5_GET(query_hca_cap_out, out, status);
- syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
- if (status) {
- DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
- "status %x, syndrome = %x", status, syndrome);
+ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
+ MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ if (!hcattr) {
attr->log_max_ft_sampler_num = 0;
- return -1;
+ return rc;
}
- hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
attr->log_max_ft_sampler_num = MLX5_GET
(flow_table_nic_cap, hcattr,
flow_table_properties_nic_receive.log_max_ft_sampler_num);
(flow_table_nic_cap, hcattr,
ft_field_support_2_nic_receive.outer_ipv4_ihl);
/* Query HCA offloads for Ethernet protocol. */
- memset(in, 0, sizeof(in));
- memset(out, 0, sizeof(out));
- MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
- MLX5_SET(query_hca_cap_in, in, op_mod,
- MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
- MLX5_HCA_CAP_OPMOD_GET_CUR);
-
- rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
- if (rc) {
- attr->eth_net_offloads = 0;
- goto error;
- }
- status = MLX5_GET(query_hca_cap_out, out, status);
- syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
- if (status) {
- DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
- "status %x, syndrome = %x", status, syndrome);
+ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
+ MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ if (!hcattr) {
attr->eth_net_offloads = 0;
- return -1;
+ return rc;
}
- hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, wqe_vlan_insert);
attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, csum_cap);
+ attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, vlan_cap);
attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
lro_cap);
+ attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, max_lso_cap);
+ attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, scatter_fcs);
attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, tunnel_lro_gre);
attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, rss_ind_tbl_cap);
/* Query HCA attribute for ROCE. */
if (attr->roce) {
- memset(in, 0, sizeof(in));
- memset(out, 0, sizeof(out));
- MLX5_SET(query_hca_cap_in, in, opcode,
- MLX5_CMD_OP_QUERY_HCA_CAP);
- MLX5_SET(query_hca_cap_in, in, op_mod,
- MLX5_GET_HCA_CAP_OP_MOD_ROCE |
- MLX5_HCA_CAP_OPMOD_GET_CUR);
- rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
- out, sizeof(out));
- if (rc)
- goto error;
- status = MLX5_GET(query_hca_cap_out, out, status);
- syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
- if (status) {
+ hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
+ MLX5_GET_HCA_CAP_OP_MOD_ROCE |
+ MLX5_HCA_CAP_OPMOD_GET_CUR);
+ if (!hcattr) {
DRV_LOG(DEBUG,
- "Failed to query devx HCA ROCE capabilities, "
- "status %x, syndrome = %x", status, syndrome);
- return -1;
+ "Failed to query devx HCA ROCE capabilities");
+ return rc;
}
- hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
}
if (attr->eth_virt &&
crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
return crypto_login_obj;
}
+
+/**
+ * Query LAG context.
+ *
+ * @param[in] ctx
+ * Pointer to ibv_context, returned from mlx5dv_open_device.
+ * @param[out] lag_ctx
+ * Pointer to struct mlx5_devx_lag_context, to be set by the routine.
+ *
+ * @return
+ * 0 on success, a negative value otherwise.
+ */
+int
+mlx5_devx_cmd_query_lag(void *ctx,
+ struct mlx5_devx_lag_context *lag_ctx)
+{
+ uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
+ uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
+ void *lctx;
+ int rc;
+
+ MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
+ rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
+ if (rc)
+ goto error;
+ lctx = MLX5_ADDR_OF(query_lag_out, out, context);
+ lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
+ fdb_selection_mode);
+ lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
+ port_select_mode);
+ lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
+ lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
+ tx_remap_affinity_2);
+ lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
+ tx_remap_affinity_1);
+ return 0;
+error:
+ rc = (rc > 0) ? -rc : rc;
+ return rc;
+}
git.droids-corp.org / dpdk.git / blobdiff