net/cnxk: update L3/L4 checksum offload in mbuf

[dpdk.git] / drivers / common / mlx5 / mlx5_devx_cmds.h

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 9c9d086..1bac18c 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -152,6 +152,8 @@ mlx5_hca_parse_graph_node_base_hdr_len_mask
 struct mlx5_hca_attr {
        uint32_t eswitch_manager:1;
        uint32_t flow_counters_dump:1;
+       uint32_t mem_rq_rmp:1;
+       uint32_t log_max_rmp:5;
        uint32_t log_max_rqt_size:5;
        uint32_t parse_graph_flex_node:1;
        uint8_t flow_counter_bulk_alloc_bitmap;
@@ -176,6 +178,7 @@ struct mlx5_hca_attr {
        uint32_t swp_csum:1;
        uint32_t swp_lso:1;
        uint32_t lro_max_msg_sz_mode:2;
+       uint32_t rq_delay_drop:1;
        uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
        uint16_t lro_min_mss_size;
        uint32_t flex_parser_protocols;
@@ -198,6 +201,7 @@ struct mlx5_hca_attr {
        uint32_t scatter_fcs_w_decap_disable:1;
        uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
        uint32_t roce:1;
+       uint32_t wait_on_time:1;
        uint32_t rq_ts_format:2;
        uint32_t sq_ts_format:2;
        uint32_t steering_format_version:4;
@@ -248,6 +252,10 @@ struct mlx5_hca_attr {
        uint32_t log_max_mmo_decompress:5;
        uint32_t umr_modify_entity_size_disabled:1;
        uint32_t umr_indirect_mkey_disabled:1;
+       uint32_t log_min_stride_wqe_sz:5;
+       uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */
+       uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */
+       uint16_t max_wqe_sz_sq;
 };
 
 /* LAG Context. */
@@ -320,6 +328,17 @@ struct mlx5_devx_modify_rq_attr {
        uint32_t lwm:16; /* Contained WQ lwm. */
 };
 
+/* Create RMP attributes structure, used by create RMP operation. */
+struct mlx5_devx_create_rmp_attr {
+       uint32_t rsvd0:8;
+       uint32_t state:4;
+       uint32_t rsvd1:20;
+       uint32_t basic_cyclic_rcv_wqe:1;
+       uint32_t rsvd4:31;
+       uint32_t rsvd8[10];
+       struct mlx5_devx_wq_attr wq_attr;
+};
+
 struct mlx5_rx_hash_field_select {
        uint32_t l3_prot_type:1;
        uint32_t l4_prot_type:1;
@@ -463,9 +482,9 @@ struct mlx5_devx_qp_attr {
        uint32_t uar_index:24;
        uint32_t cqn:24;
        uint32_t log_page_size:5;
-       uint32_t rq_size:17; /* Must be power of 2. */
+       uint32_t num_of_receive_wqes:17; /* Must be power of 2. */
        uint32_t log_rq_stride:3;
-       uint32_t sq_size:17; /* Must be power of 2. */
+       uint32_t num_of_send_wqbbs:17; /* Must be power of 2. */
        uint32_t ts_format:2;
        uint32_t dbr_umem_valid:1;
        uint32_t dbr_umem_id;
@@ -597,6 +616,9 @@ __rte_internal
 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
                            struct mlx5_devx_modify_rq_attr *rq_attr);
 __rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx,
+                       struct mlx5_devx_create_rmp_attr *rq_attr, int socket);
+__rte_internal
 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
                                           struct mlx5_devx_tir_attr *tir_attr);
 __rte_internal