net/hns3: delete redundant xstats RAS statistics

[dpdk.git] / drivers / common / mlx5 / mlx5_devx_cmds.h

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index bf83a90..2826c0b 100644 (file)
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -38,11 +38,17 @@ struct mlx5_devx_mkey_attr {
 /* HCA qos attributes. */
 struct mlx5_hca_qos_attr {
        uint32_t sup:1; /* Whether QOS is supported. */
-       uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
+       uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */
        uint32_t packet_pacing:1; /* Packet pacing is supported. */
        uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
-       uint32_t flow_meter_reg_share:1;
-       /* Whether reg_c share is supported. */
+       uint32_t flow_meter:1;
+       /*
+        * Flow meter is supported, updated version.
+        * When flow_meter is 1, it indicates that REG_C sharing is supported.
+        * If flow_meter is 1, flow_meter_old is also 1.
+        * Using older driver versions, flow_meter_old can be 1
+        * while flow_meter is 0.
+        */
        uint8_t log_max_flow_meter;
        /* Power of the maximum supported meters. */
        uint8_t flow_meter_reg_c_ids;
@@ -115,10 +121,18 @@ struct mlx5_hca_attr {
        uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
        uint32_t scatter_fcs_w_decap_disable:1;
        uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
+       uint32_t roce:1;
+       uint32_t rq_ts_format:2;
+       uint32_t sq_ts_format:2;
+       uint32_t qp_ts_format:2;
        uint32_t regex:1;
+       uint32_t reg_c_preserve:1;
        uint32_t regexp_num_of_engines;
        uint32_t log_max_ft_sampler_num:8;
        uint32_t geneve_tlv_opt;
+       uint32_t cqe_compression:1;
+       uint32_t mini_cqe_resp_flow_tag:1;
+       uint32_t mini_cqe_resp_l3_l4_tag:1;
        struct mlx5_hca_qos_attr qos;
        struct mlx5_hca_vdpa_attr vdpa;
        int log_max_qp_sz;
@@ -130,6 +144,13 @@ struct mlx5_hca_attr {
        uint32_t log_max_srq;
        uint32_t log_max_srq_sz;
        uint32_t rss_ind_tbl_cap;
+       uint32_t mmo_dma_en:1;
+       uint32_t mmo_compress_en:1;
+       uint32_t mmo_decompress_en:1;
+       uint32_t compress_min_block_size:4;
+       uint32_t log_max_mmo_dma:5;
+       uint32_t log_max_mmo_compress:5;
+       uint32_t log_max_mmo_decompress:5;
 };
 
 struct mlx5_devx_wq_attr {
@@ -171,6 +192,7 @@ struct mlx5_devx_create_rq_attr {
        uint32_t state:4;
        uint32_t flush_in_error_en:1;
        uint32_t hairpin:1;
+       uint32_t ts_format:2;
        uint32_t user_index:24;
        uint32_t cqn:24;
        uint32_t counter_set_id:8;
@@ -254,6 +276,7 @@ struct mlx5_devx_create_sq_attr {
        uint32_t hairpin:1;
        uint32_t non_wire:1;
        uint32_t static_sq_wq:1;
+       uint32_t ts_format:2;
        uint32_t user_index:24;
        uint32_t cqn:24;
        uint32_t packet_pacing_rate_limit_index:16;
@@ -337,6 +360,7 @@ struct mlx5_devx_qp_attr {
        uint32_t rq_size:17; /* Must be power of 2. */
        uint32_t log_rq_stride:3;
        uint32_t sq_size:17; /* Must be power of 2. */
+       uint32_t ts_format:2;
        uint32_t dbr_umem_valid:1;
        uint32_t dbr_umem_id;
        uint64_t dbr_address;
@@ -522,4 +546,13 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
 
 __rte_internal
 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
+
+__rte_internal
+int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id);
+
+__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx);
+__rte_internal
+int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
+                                     uint32_t *out_of_buffers);
 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */