uint64_t doorbell_bar_offset;
};
+struct mlx5_hca_flow_attr {
+ uint32_t tunnel_header_0_1;
+ uint32_t tunnel_header_2_3;
+};
+
/* HCA supports this number of time periods for LRO. */
#define MLX5_LRO_NUM_SUPP_PERIODS 4
uint32_t eth_net_offloads:1;
uint32_t eth_virt:1;
uint32_t wqe_vlan_insert:1;
+ uint32_t csum_cap:1;
uint32_t wqe_inline_mode:2;
uint32_t vport_inline_mode:3;
uint32_t tunnel_stateless_geneve_rx:1;
uint32_t roce:1;
uint32_t rq_ts_format:2;
uint32_t sq_ts_format:2;
+ uint32_t steering_format_version:4;
uint32_t qp_ts_format:2;
uint32_t regex:1;
uint32_t reg_c_preserve:1;
+ uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */
uint32_t crypto:1; /* Crypto engine is supported. */
uint32_t aes_xts:1; /* AES-XTS crypto is supported. */
uint32_t dek:1; /* General obj type DEK is supported. */
uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */
uint32_t regexp_num_of_engines;
uint32_t log_max_ft_sampler_num:8;
+ uint32_t inner_ipv4_ihl:1;
+ uint32_t outer_ipv4_ihl:1;
uint32_t geneve_tlv_opt;
uint32_t cqe_compression:1;
uint32_t mini_cqe_resp_flow_tag:1;
uint32_t mini_cqe_resp_l3_l4_tag:1;
+ uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
struct mlx5_hca_qos_attr qos;
struct mlx5_hca_vdpa_attr vdpa;
+ struct mlx5_hca_flow_attr flow;
int log_max_qp_sz;
int log_max_cq_sz;
int log_max_qp;
int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
uint32_t arg, uint32_t *data, uint32_t dw_cnt);
+__rte_internal
+int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id,
+ uint32_t arg, uint32_t *data, uint32_t dw_cnt);
+
__rte_internal
struct mlx5_devx_obj *
mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
__rte_internal
int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
uint32_t *out_of_buffers);
+__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx,
+ uint32_t pd, uint32_t log_obj_size);
+
/**
* Create general object of type FLOW_METER_ASO using DevX API..
*