net/ice/base: cleanup filter list on error

[dpdk.git] / drivers / common / mlx5 / mlx5_prm.h

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 751dda2..01a039f 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -901,6 +901,8 @@ enum {
        MLX5_CMD_OP_SUSPEND_QP = 0x50F,
        MLX5_CMD_OP_RESUME_QP = 0x510,
        MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
+       MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
+       MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
        MLX5_CMD_OP_ALLOC_PD = 0x800,
        MLX5_CMD_OP_DEALLOC_PD = 0x801,
        MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
@@ -911,6 +913,7 @@ enum {
        MLX5_CMD_OP_MODIFY_SQ = 0X905,
        MLX5_CMD_OP_CREATE_RQ = 0x908,
        MLX5_CMD_OP_MODIFY_RQ = 0x909,
+       MLX5_CMD_OP_QUERY_RQ = 0x90b,
        MLX5_CMD_OP_CREATE_TIS = 0x912,
        MLX5_CMD_OP_QUERY_TIS = 0x915,
        MLX5_CMD_OP_CREATE_RQT = 0x916,
@@ -1444,7 +1447,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8 max_geneve_tlv_options[0x8];
        u8 reserved_at_568[0x3];
        u8 max_geneve_tlv_option_data_len[0x5];
-       u8 reserved_at_570[0x4c];
+       u8 reserved_at_570[0x49];
+       u8 mini_cqe_resp_l3_l4_tag[0x1];
+       u8 mini_cqe_resp_flow_tag[0x1];
+       u8 enhanced_cqe_compression[0x1];
        u8 mini_cqe_resp_stride_index[0x1];
        u8 cqe_128_always[0x1];
        u8 cqe_compression_128[0x1];
@@ -1887,6 +1893,24 @@ struct mlx5_ifc_modify_rq_out_bits {
        u8 reserved_at_40[0x40];
 };
 
+struct mlx5_ifc_query_rq_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_40[0xc0];
+       struct mlx5_ifc_rqc_bits rq_context;
+};
+
+struct mlx5_ifc_query_rq_in_bits {
+       u8 opcode[0x10];
+       u8 reserved_at_10[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x8];
+       u8 rqn[0x18];
+       u8 reserved_at_60[0x20];
+};
+
 struct mlx5_ifc_create_tis_out_bits {
        u8 status[0x8];
        u8 reserved_at_8[0x18];
@@ -3191,6 +3215,85 @@ struct mlx5_ifc_query_regexp_register_out_bits {
        u8 register_data[0x20];
 };
 
+/* Queue counters. */
+struct mlx5_ifc_alloc_q_counter_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_40[0x18];
+       u8 counter_set_id[0x8];
+       u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_alloc_q_counter_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_query_q_counter_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_40[0x40];
+       u8 rx_write_requests[0x20];
+       u8 reserved_at_a0[0x20];
+       u8 rx_read_requests[0x20];
+       u8 reserved_at_e0[0x20];
+       u8 rx_atomic_requests[0x20];
+       u8 reserved_at_120[0x20];
+       u8 rx_dct_connect[0x20];
+       u8 reserved_at_160[0x20];
+       u8 out_of_buffer[0x20];
+       u8 reserved_at_1a0[0x20];
+       u8 out_of_sequence[0x20];
+       u8 reserved_at_1e0[0x20];
+       u8 duplicate_request[0x20];
+       u8 reserved_at_220[0x20];
+       u8 rnr_nak_retry_err[0x20];
+       u8 reserved_at_260[0x20];
+       u8 packet_seq_err[0x20];
+       u8 reserved_at_2a0[0x20];
+       u8 implied_nak_seq_err[0x20];
+       u8 reserved_at_2e0[0x20];
+       u8 local_ack_timeout_err[0x20];
+       u8 reserved_at_320[0xa0];
+       u8 resp_local_length_error[0x20];
+       u8 req_local_length_error[0x20];
+       u8 resp_local_qp_error[0x20];
+       u8 local_operation_error[0x20];
+       u8 resp_local_protection[0x20];
+       u8 req_local_protection[0x20];
+       u8 resp_cqe_error[0x20];
+       u8 req_cqe_error[0x20];
+       u8 req_mw_binding[0x20];
+       u8 req_bad_response[0x20];
+       u8 req_remote_invalid_request[0x20];
+       u8 resp_remote_invalid_request[0x20];
+       u8 req_remote_access_errors[0x20];
+       u8 resp_remote_access_errors[0x20];
+       u8 req_remote_operation_errors[0x20];
+       u8 req_transport_retries_exceeded[0x20];
+       u8 cq_overflow[0x20];
+       u8 resp_cqe_flush_error[0x20];
+       u8 req_cqe_flush_error[0x20];
+       u8 reserved_at_620[0x1e0];
+};
+
+struct mlx5_ifc_query_q_counter_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 reserved_at_20[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_40[0x80];
+       u8 clear[0x1];
+       u8 reserved_at_c1[0x1f];
+       u8 reserved_at_e0[0x18];
+       u8 counter_set_id[0x8];
+};
+
 /* CQE format mask. */
 #define MLX5E_CQE_FORMAT_MASK 0xc