uint8_t op_own;
};
+/* GGA */
/* MMO metadata segment */
-#define MLX5_OPCODE_MMO 0x2f
-#define MLX5_OPC_MOD_MMO_REGEX 0x4
+#define MLX5_OPCODE_MMO 0x2fu
+#define MLX5_OPC_MOD_MMO_REGEX 0x4u
+#define MLX5_OPC_MOD_MMO_COMP 0x2u
+#define MLX5_OPC_MOD_MMO_DECOMP 0x3u
+#define MLX5_OPC_MOD_MMO_DMA 0x1u
+
+#define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
+#define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
+#define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
+#define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
+#define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
+#define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
+#define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
+#define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
struct mlx5_wqe_metadata_seg {
uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
uint64_t addr;
};
+struct mlx5_gga_wqe {
+ uint32_t opcode;
+ uint32_t sq_ds;
+ uint32_t flags;
+ uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */
+ uint32_t gga_ctrl2;
+ uint32_t opaque_lkey;
+ uint64_t opaque_vaddr;
+ struct mlx5_wqe_dseg gather;
+ struct mlx5_wqe_dseg scatter;
+} __rte_packed;
+
+struct mlx5_gga_compress_opaque {
+ uint32_t syndrom;
+ uint32_t reserved0;
+ uint32_t scattered_length;
+ uint32_t gathered_length;
+ uint64_t scatter_crc;
+ uint64_t gather_crc;
+ uint32_t crc32;
+ uint32_t adler32;
+ uint8_t reserved1[216];
+} __rte_packed;
+
struct mlx5_ifc_regexp_mmo_control_bits {
uint8_t reserved_at_31[0x2];
uint8_t le[0x1];
MLX5_MODI_IN_TCP_SEQ_NUM,
MLX5_MODI_OUT_TCP_ACK_NUM,
MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
+ MLX5_MODI_GTP_TEID = 0x6E,
};
/* Total number of metadata reg_c's. */
#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
-#define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
+#define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
(&(__mlx5_nullp(typ)->fld)))
#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
(__mlx5_bit_off(typ, fld) & 0x1f))
u8 icmp_code[0x8];
u8 icmpv6_type[0x8];
u8 icmpv6_code[0x8];
- u8 reserved_at_120[0x20];
+ u8 geneve_tlv_option_0_data[0x20];
u8 gtpu_teid[0x20];
u8 gtpu_msg_type[0x08];
u8 gtpu_msg_flags[0x08];
- u8 reserved_at_170[0x90];
+ u8 reserved_at_170[0x10];
+ u8 gtpu_dw_2[0x20];
+ u8 gtpu_first_ext_dw_0[0x20];
+ u8 gtpu_dw_0[0x20];
+ u8 reserved_at_240[0x20];
+
};
struct mlx5_ifc_fte_match_set_misc4_bits {
#endif
};
+struct mlx5_ifc_dest_format_struct_bits {
+ u8 destination_type[0x8];
+ u8 destination_id[0x18];
+ u8 reserved_0[0x20];
+};
+
enum {
MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
MLX5_CMD_OP_SUSPEND_QP = 0x50F,
MLX5_CMD_OP_RESUME_QP = 0x510,
MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
+ MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
+ MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
MLX5_CMD_OP_ALLOC_PD = 0x800,
MLX5_CMD_OP_DEALLOC_PD = 0x801,
MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
MLX5_CMD_OP_MODIFY_SQ = 0X905,
MLX5_CMD_OP_CREATE_RQ = 0x908,
MLX5_CMD_OP_MODIFY_RQ = 0x909,
+ MLX5_CMD_OP_QUERY_RQ = 0x90b,
MLX5_CMD_OP_CREATE_TIS = 0x912,
MLX5_CMD_OP_QUERY_TIS = 0x915,
MLX5_CMD_OP_CREATE_RQT = 0x916,
(1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
#define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
+#define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
+ (1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT)
enum {
MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_0[0x30];
u8 vhca_id[0x10];
- u8 reserved_at_40[0x40];
+ u8 reserved_at_40[0x20];
+ u8 reserved_at_60[0x3];
+ u8 log_regexp_scatter_gather_size[0x5];
+ u8 reserved_at_68[0x3];
+ u8 log_dma_mmo_size[0x5];
+ u8 reserved_at_70[0x3];
+ u8 log_compress_mmo_size[0x5];
+ u8 reserved_at_78[0x3];
+ u8 log_decompress_mmo_size[0x5];
u8 log_max_srq_sz[0x8];
u8 log_max_qp_sz[0x8];
u8 reserved_at_90[0x9];
u8 regexp[0x1];
u8 reserved_at_a1[0x3];
u8 regexp_num_of_engines[0x4];
- u8 reserved_at_a8[0x3];
+ u8 reserved_at_a8[0x1];
+ u8 reg_c_preserve[0x1];
+ u8 reserved_at_aa[0x1];
u8 log_max_srq[0x5];
u8 reserved_at_b0[0x3];
u8 regexp_log_crspace_size[0x5];
u8 log_max_ra_res_dc[0x6];
u8 reserved_at_140[0xa];
u8 log_max_ra_req_qp[0x6];
- u8 reserved_at_150[0xa];
+ u8 rtr2rts_qp_counters_set_id[0x1];
+ u8 rts2rts_udp_sport[0x1];
+ u8 rts2rts_lag_tx_port_affinity[0x1];
+ u8 dma_mmo[0x1];
+ u8 compress_min_block_size[0x4];
+ u8 compress[0x1];
+ u8 decompress[0x1];
u8 log_max_ra_res_qp[0x6];
u8 end_pad[0x1];
u8 cc_query_allowed[0x1];
u8 reserved_at_500[0x20];
u8 num_of_uars_per_page[0x20];
u8 flex_parser_protocols[0x20];
- u8 reserved_at_560[0x20];
- u8 reserved_at_580[0x3c];
+ u8 max_geneve_tlv_options[0x8];
+ u8 reserved_at_568[0x3];
+ u8 max_geneve_tlv_option_data_len[0x5];
+ u8 reserved_at_570[0x49];
+ u8 mini_cqe_resp_l3_l4_tag[0x1];
+ u8 mini_cqe_resp_flow_tag[0x1];
+ u8 enhanced_cqe_compression[0x1];
u8 mini_cqe_resp_stride_index[0x1];
u8 cqe_128_always[0x1];
u8 cqe_compression_128[0x1];
u8 reserved_at_4[0x1];
u8 packet_pacing_burst_bound[0x1];
u8 packet_pacing_typical_size[0x1];
- u8 flow_meter_srtcm[0x1];
+ u8 flow_meter_old[0x1];
u8 reserved_at_8[0x8];
u8 log_max_flow_meter[0x8];
u8 flow_meter_reg_id[0x8];
u8 wqe_rate_pp[0x1];
u8 reserved_at_25[0x7];
- u8 flow_meter_reg_share[0x1];
+ u8 flow_meter[0x1];
u8 reserved_at_2e[0x17];
u8 packet_pacing_max_rate[0x20];
u8 packet_pacing_min_rate[0x20];
u8 reserved_at_40[0x40];
};
+struct mlx5_ifc_query_rq_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0xc0];
+ struct mlx5_ifc_rqc_bits rq_context;
+};
+
+struct mlx5_ifc_query_rq_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_at_10[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 rqn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
struct mlx5_ifc_create_tis_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
};
enum {
+ MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
u8 reserved_at_180[0x50];
};
+struct mlx5_ifc_geneve_tlv_option_bits {
+ u8 modify_field_select[0x40];
+ u8 reserved_at_40[0x18];
+ u8 geneve_option_fte_index[0x8];
+ u8 option_class[0x10];
+ u8 option_type[0x8];
+ u8 reserved_at_78[0x3];
+ u8 option_data_length[0x5];
+ u8 reserved_at_80[0x180];
+};
+
struct mlx5_ifc_create_virtio_q_counters_in_bits {
struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
};
+
+struct mlx5_ifc_create_geneve_tlv_option_in_bits {
+ struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+ struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
+};
+
enum {
MLX5_VIRTQ_STATE_INIT = 0,
MLX5_VIRTQ_STATE_RDY = 1,
u8 counter_set_id[0x20];
u8 reserved_at_320[0x8];
u8 pd[0x18];
- u8 reserved_at_340[0xc0];
+ u8 reserved_at_340[0x2];
+ u8 queue_period_mode[0x2];
+ u8 queue_period_us[0xc];
+ u8 queue_max_count[0x10];
+ u8 reserved_at_360[0xa0];
};
struct mlx5_ifc_virtio_net_q_bits {
u8 register_data[0x20];
};
+/* Queue counters. */
+struct mlx5_ifc_alloc_q_counter_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x18];
+ u8 counter_set_id[0x8];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_alloc_q_counter_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_query_q_counter_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+ u8 rx_write_requests[0x20];
+ u8 reserved_at_a0[0x20];
+ u8 rx_read_requests[0x20];
+ u8 reserved_at_e0[0x20];
+ u8 rx_atomic_requests[0x20];
+ u8 reserved_at_120[0x20];
+ u8 rx_dct_connect[0x20];
+ u8 reserved_at_160[0x20];
+ u8 out_of_buffer[0x20];
+ u8 reserved_at_1a0[0x20];
+ u8 out_of_sequence[0x20];
+ u8 reserved_at_1e0[0x20];
+ u8 duplicate_request[0x20];
+ u8 reserved_at_220[0x20];
+ u8 rnr_nak_retry_err[0x20];
+ u8 reserved_at_260[0x20];
+ u8 packet_seq_err[0x20];
+ u8 reserved_at_2a0[0x20];
+ u8 implied_nak_seq_err[0x20];
+ u8 reserved_at_2e0[0x20];
+ u8 local_ack_timeout_err[0x20];
+ u8 reserved_at_320[0xa0];
+ u8 resp_local_length_error[0x20];
+ u8 req_local_length_error[0x20];
+ u8 resp_local_qp_error[0x20];
+ u8 local_operation_error[0x20];
+ u8 resp_local_protection[0x20];
+ u8 req_local_protection[0x20];
+ u8 resp_cqe_error[0x20];
+ u8 req_cqe_error[0x20];
+ u8 req_mw_binding[0x20];
+ u8 req_bad_response[0x20];
+ u8 req_remote_invalid_request[0x20];
+ u8 resp_remote_invalid_request[0x20];
+ u8 req_remote_access_errors[0x20];
+ u8 resp_remote_access_errors[0x20];
+ u8 req_remote_operation_errors[0x20];
+ u8 req_transport_retries_exceeded[0x20];
+ u8 cq_overflow[0x20];
+ u8 resp_cqe_flush_error[0x20];
+ u8 req_cqe_flush_error[0x20];
+ u8 reserved_at_620[0x1e0];
+};
+
+struct mlx5_ifc_query_q_counter_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x80];
+ u8 clear[0x1];
+ u8 reserved_at_c1[0x1f];
+ u8 reserved_at_e0[0x18];
+ u8 counter_set_id[0x8];
+};
+
/* CQE format mask. */
#define MLX5E_CQE_FORMAT_MASK 0xc
git.droids-corp.org / dpdk.git / blobdiff