#define MLX5_OPCODE_WAIT 0x0fu
#endif
+#define MLX5_OPC_MOD_WAIT_CQ_PI 0u
+#define MLX5_OPC_MOD_WAIT_DATA 1u
+#define MLX5_OPC_MOD_WAIT_TIME 2u
+
+
+#define MLX5_WAIT_COND_INVERT 0x10u
+#define MLX5_WAIT_COND_ALWAYS_TRUE 0u
+#define MLX5_WAIT_COND_EQUAL 1u
+#define MLX5_WAIT_COND_BIGGER 2u
+#define MLX5_WAIT_COND_SMALLER 3u
+#define MLX5_WAIT_COND_CYCLIC_BIGGER 4u
+#define MLX5_WAIT_COND_CYCLIC_SMALLER 5u
+
#ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
#define MLX5_OPCODE_ACCESS_ASO 0x2du
#endif
/* Maximum number of DS in WQE. Limited by 6-bit field. */
#define MLX5_DSEG_MAX 63
+/* The 32 bit syndrome offset in struct mlx5_err_cqe. */
+#define MLX5_ERROR_CQE_SYNDROME_OFFSET 52
+
/* The completion mode offset in the WQE control segment line 2. */
#define MLX5_COMP_MODE_OFFSET 2
/* The maximum log value of segments per RQ WQE. */
#define MLX5_MAX_LOG_RQ_SEGS 5u
+/* Log 2 of the default size of a WQE for Multi-Packet RQ. */
+#define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U
+
/* The alignment needed for WQ buffer. */
#define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
uint32_t qpn_cqn;
} __rte_packed;
+struct mlx5_wqe_wseg {
+ uint32_t operation;
+ uint32_t lkey;
+ uint32_t va_high;
+ uint32_t va_low;
+ uint64_t value;
+ uint64_t mask;
+} __rte_packed;
+
/* The title WQEBB, header of WQE. */
struct mlx5_wqe {
union {
#define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
#define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
#define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
+#define MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE 0x29D0084
+#define MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE 0x29D0011
struct mlx5_wqe_metadata_seg {
uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
MLX5_CMD_OP_CREATE_RQ = 0x908,
MLX5_CMD_OP_MODIFY_RQ = 0x909,
MLX5_CMD_OP_QUERY_RQ = 0x90b,
+ MLX5_CMD_OP_CREATE_RMP = 0x90c,
+ MLX5_CMD_OP_MODIFY_RMP = 0x90d,
+ MLX5_CMD_OP_DESTROY_RMP = 0x90e,
+ MLX5_CMD_OP_QUERY_RMP = 0x90f,
MLX5_CMD_OP_CREATE_TIS = 0x912,
MLX5_CMD_OP_QUERY_TIS = 0x915,
MLX5_CMD_OP_CREATE_RQT = 0x916,
MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
+ MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1,
MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
#define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
struct mlx5_ifc_cmd_hca_cap_bits {
- u8 reserved_at_0[0x30];
+ u8 reserved_at_0[0x20];
+ u8 hca_cap_2[0x1];
+ u8 reserved_at_21[0xf];
u8 vhca_id[0x10];
u8 reserved_at_40[0x20];
u8 reserved_at_60[0x3];
u8 reserved_at_bc[0x4];
u8 reserved_at_c0[0x8];
u8 log_max_cq_sz[0x8];
- u8 reserved_at_d0[0xb];
+ u8 reserved_at_d0[0x2];
+ u8 access_register_user[0x1];
+ u8 reserved_at_d3[0x8];
u8 log_max_cq[0x5];
u8 log_max_eq_sz[0x8];
u8 relaxed_ordering_write[0x1];
u8 relaxed_ordering_read[0x1];
- u8 access_register_user[0x1];
- u8 log_max_mkey[0x5];
+ u8 log_max_mkey[0x6];
u8 reserved_at_f0[0x8];
u8 dump_fill_mkey[0x1];
u8 reserved_at_f9[0x3];
u8 reserved_at_378[0x3];
u8 log_max_tis[0x5];
u8 basic_cyclic_rcv_wqe[0x1];
- u8 reserved_at_381[0x2];
+ u8 reserved_at_381[0x1];
+ u8 mem_rq_rmp[0x1];
u8 log_max_rmp[0x5];
u8 reserved_at_388[0x3];
u8 log_max_rqt[0x5];
u8 num_vhca_ports[0x8];
u8 reserved_at_618[0x6];
u8 sw_owner_id[0x1];
- u8 reserved_at_61f[0x109];
+ u8 reserved_at_61f[0x6C];
+ u8 wait_on_data[0x1];
+ u8 wait_on_time[0x1];
+ u8 reserved_at_68d[0xBB];
u8 dma_mmo_qp[0x1];
u8 regexp_mmo_qp[0x1];
u8 compress_mmo_qp[0x1];
u8 max_reformat_insert_offset[0x8];
u8 max_reformat_remove_size[0x8];
u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
- u8 aso_conntrack_reg_id[0x8];
+ u8 reserved_at_c0[0x3];
+ u8 log_min_stride_wqe_sz[0x5];
u8 reserved_at_c8[0x3];
u8 log_conn_track_granularity[0x5];
u8 reserved_at_d0[0x3];
u8 reserved_at_100[0x700];
};
+struct mlx5_ifc_esw_cap_bits {
+ u8 reserved_at_0[0x60];
+
+ u8 esw_manager_vport_number_valid[0x1];
+ u8 reserved_at_61[0xf];
+ u8 esw_manager_vport_number[0x10];
+
+ u8 reserved_at_80[0x780];
+};
+
union mlx5_ifc_hca_cap_union_bits {
struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
+ struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
struct mlx5_ifc_per_protocol_networking_offload_caps_bits
per_protocol_networking_offload_caps;
struct mlx5_ifc_qos_cap_bits qos_cap;
struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
+ struct mlx5_ifc_esw_cap_bits esw_cap;
struct mlx5_ifc_roce_caps_bits roce_caps;
u8 reserved_at_0[0x8000];
};
u8 reserved_at_60[0x20];
};
+enum {
+ MLX5_RMPC_STATE_RDY = 0x1,
+ MLX5_RMPC_STATE_ERR = 0x3,
+};
+
+struct mlx5_ifc_rmpc_bits {
+ u8 reserved_at_0[0x8];
+ u8 state[0x4];
+ u8 reserved_at_c[0x14];
+ u8 basic_cyclic_rcv_wqe[0x1];
+ u8 reserved_at_21[0x1f];
+ u8 reserved_at_40[0x140];
+ struct mlx5_ifc_wq_bits wq;
+};
+
+struct mlx5_ifc_query_rmp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0xc0];
+ struct mlx5_ifc_rmpc_bits rmp_context;
+};
+
+struct mlx5_ifc_query_rmp_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_at_10[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 rmpn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_modify_rmp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_rmp_bitmask_bits {
+ u8 reserved_at_0[0x20];
+ u8 reserved_at_20[0x1f];
+ u8 lwm[0x1];
+};
+
+struct mlx5_ifc_modify_rmp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 rmp_state[0x4];
+ u8 reserved_at_44[0x4];
+ u8 rmpn[0x18];
+ u8 reserved_at_60[0x20];
+ struct mlx5_ifc_rmp_bitmask_bits bitmask;
+ u8 reserved_at_c0[0x40];
+ struct mlx5_ifc_rmpc_bits ctx;
+};
+
+struct mlx5_ifc_create_rmp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x8];
+ u8 rmpn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_create_rmp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0xc0];
+ struct mlx5_ifc_rmpc_bits ctx;
+};
+
struct mlx5_ifc_create_tis_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
* timestamp format supported by the queue.
*
* @return
- * Converted timstamp format settings.
+ * Converted timestamp format settings.
*/
static inline uint32_t
mlx5_ts_format_conv(uint32_t ts_format)
git.droids-corp.org / dpdk.git / blobdiff