u8 vxlan_vni[0x18];
u8 reserved_at_b8[0x8];
u8 geneve_vni[0x18];
- u8 reserved_at_e4[0x7];
+ u8 reserved_at_e4[0x6];
+ u8 geneve_tlv_option_0_exist[0x1];
u8 geneve_oam[0x1];
u8 reserved_at_e0[0xc];
u8 outer_ipv6_flow_label[0x14];
u8 prog_sample_field_id_2[0x20];
u8 prog_sample_field_value_3[0x20];
u8 prog_sample_field_id_3[0x20];
- u8 reserved_at_100[0x100];
+ u8 prog_sample_field_value_4[0x20];
+ u8 prog_sample_field_id_4[0x20];
+ u8 prog_sample_field_value_5[0x20];
+ u8 prog_sample_field_id_5[0x20];
+ u8 prog_sample_field_value_6[0x20];
+ u8 prog_sample_field_id_6[0x20];
+ u8 prog_sample_field_value_7[0x20];
+ u8 prog_sample_field_id_7[0x20];
};
struct mlx5_ifc_fte_match_set_misc5_bits {
MLX5_CMD_OP_DEALLOC_PD = 0x801,
MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
+ MLX5_CMD_OP_QUERY_LAG = 0x842,
MLX5_CMD_OP_CREATE_TIR = 0x900,
MLX5_CMD_OP_MODIFY_TIR = 0x901,
MLX5_CMD_OP_CREATE_SQ = 0X904,
MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
+ MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
};
u8 wqe_index_ignore_cap[0x1];
u8 dynamic_qp_allocation[0x1];
u8 log_max_qp[0x5];
- u8 regexp[0x1];
- u8 reserved_at_a1[0x3];
+ u8 reserved_at_a0[0x4];
u8 regexp_num_of_engines[0x4];
u8 reserved_at_a8[0x1];
u8 reg_c_preserve[0x1];
u8 reserved_at_aa[0x1];
u8 log_max_srq[0x5];
- u8 reserved_at_b0[0x3];
- u8 regexp_log_crspace_size[0x5];
- u8 reserved_at_b8[0x3];
+ u8 reserved_at_b0[0xb];
u8 scatter_fcs_w_decap_disable[0x1];
u8 reserved_at_bc[0x4];
u8 reserved_at_c0[0x8];
u8 rtr2rts_qp_counters_set_id[0x1];
u8 rts2rts_udp_sport[0x1];
u8 rts2rts_lag_tx_port_affinity[0x1];
- u8 dma_mmo[0x1];
+ u8 dma_mmo_sq[0x1];
u8 compress_min_block_size[0x4];
- u8 compress[0x1];
- u8 decompress[0x1];
+ u8 compress_mmo_sq[0x1];
+ u8 decompress_mmo_sq[0x1];
u8 log_max_ra_res_qp[0x6];
u8 end_pad[0x1];
u8 cc_query_allowed[0x1];
u8 uc[0x1];
u8 rc[0x1];
u8 uar_4k[0x1];
- u8 reserved_at_241[0x9];
+ u8 reserved_at_241[0x8];
+ u8 regexp_params[0x1];
u8 uar_sz[0x6];
- u8 reserved_at_250[0x8];
+ u8 port_selection_cap[0x1];
+ u8 reserved_at_251[0x7];
u8 log_pg_sz[0x8];
u8 bf[0x1];
u8 driver_version[0x1];
u8 num_lag_ports[0x4];
u8 reserved_at_280[0x10];
u8 max_wqe_sz_sq[0x10];
- u8 reserved_at_2a0[0x10];
+ u8 reserved_at_2a0[0xc];
+ u8 regexp_mmo_sq[0x1];
+ u8 regexp_version[0x3];
u8 max_wqe_sz_rq[0x10];
u8 max_flow_counter_31_16[0x10];
u8 max_wqe_sz_sq_dc[0x10];
u8 num_vhca_ports[0x8];
u8 reserved_at_618[0x6];
u8 sw_owner_id[0x1];
- u8 reserved_at_61f[0x1e1];
+ u8 reserved_at_61f[0x109];
+ u8 dma_mmo_qp[0x1];
+ u8 regexp_mmo_qp[0x1];
+ u8 compress_mmo_qp[0x1];
+ u8 decompress_mmo_qp[0x1];
+ u8 reserved_at_624[0xd4];
};
struct mlx5_ifc_qos_cap_bits {
u8 reserved_at_1c0[0x620];
};
+/**
+ * PARSE_GRAPH_NODE Capabilities Field Descriptions
+ */
+struct mlx5_ifc_parse_graph_node_cap_bits {
+ u8 node_in[0x20];
+ u8 node_out[0x20];
+ u8 header_length_mode[0x10];
+ u8 sample_offset_mode[0x10];
+ u8 max_num_arc_in[0x08];
+ u8 max_num_arc_out[0x08];
+ u8 max_num_sample[0x08];
+ u8 reserved_at_78[0x07];
+ u8 sample_id_in_out[0x1];
+ u8 max_base_header_length[0x10];
+ u8 reserved_at_90[0x08];
+ u8 max_sample_base_offset[0x08];
+ u8 max_next_header_offset[0x10];
+ u8 reserved_at_b0[0x08];
+ u8 header_length_mask_width[0x08];
+};
+
struct mlx5_ifc_flow_table_prop_layout_bits {
u8 ft_support[0x1];
u8 flow_tag[0x1];
ft_field_support_2_nic_receive;
};
+/*
+ * HCA Capabilities 2
+ */
struct mlx5_ifc_cmd_hca_cap_2_bits {
u8 reserved_at_0[0x80]; /* End of DW4. */
- u8 reserved_at_80[0xb];
+ u8 reserved_at_80[0x3];
+ u8 max_num_prog_sample_field[0x5];
+ u8 reserved_at_88[0x3];
u8 log_max_num_reserved_qpn[0x5];
u8 reserved_at_90[0x3];
u8 log_reserved_qpn_granularity[0x5];
u8 reserved_at_68[0x18];
};
+/*
+ * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa.
+ * Each TIS binds to one PF by setting lag_tx_port_affinity (>0).
+ * Once LAG enabled, we create multiple TISs and bind each one to
+ * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1.
+ */
+#define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \
+ (index) % (num) + 1 : 0)
struct mlx5_ifc_tisc_bits {
u8 strict_lag_tx_port_affinity[0x1];
u8 reserved_at_1[0x3];
u8 reserved_at_60[0x20];
};
+/* port_select_mode definition. */
+enum mlx5_lag_mode_type {
+ MLX5_LAG_MODE_TIS = 0,
+ MLX5_LAG_MODE_HASH = 1,
+};
+
+struct mlx5_ifc_lag_context_bits {
+ u8 fdb_selection_mode[0x1];
+ u8 reserved_at_1[0x14];
+ u8 port_select_mode[0x3];
+ u8 reserved_at_18[0x5];
+ u8 lag_state[0x3];
+ u8 reserved_at_20[0x14];
+ u8 tx_remap_affinity_2[0x4];
+ u8 reserved_at_38[0x4];
+ u8 tx_remap_affinity_1[0x4];
+};
+
+struct mlx5_ifc_query_lag_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_query_lag_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ struct mlx5_ifc_lag_context_bits context;
+};
+
struct mlx5_ifc_alloc_transport_domain_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 reserved_at_60[0x20];
};
+struct mlx5_ifc_qpc_extension_bits {
+ u8 reserved_at_0[0x2];
+ u8 mmo[0x1];
+ u8 reserved_at_3[0x5fd];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_pas_list_bits {
+ u8 pas[0][0x40];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_extension_and_pas_list_bits {
+ struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
+ u8 pas[0][0x40];
+};
+
+
#ifdef PEDANTIC
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
u8 uid[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
- u8 reserved_at_40[0x40];
+ u8 qpc_ext[0x1];
+ u8 reserved_at_41[0x3f];
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
struct mlx5_ifc_qpc_bits qpc;
u8 wq_umem_id[0x20];
u8 wq_umem_valid[0x1];
u8 reserved_at_861[0x1f];
- u8 pas[0][0x40];
+ union {
+ struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
+ struct mlx5_ifc_qpc_extension_and_pas_list_bits
+ qpc_extension_and_pas_list;
+ };
};
#ifdef PEDANTIC
#pragma GCC diagnostic error "-Wpedantic"
};
struct regexp_params_field_select_bits {
- u8 reserved_at_0[0x1e];
+ u8 reserved_at_0[0x1d];
+ u8 rof_mkey[0x1];
u8 stop_engine[0x1];
- u8 db_umem_id[0x1];
+ u8 reserved_at_1f[0x1];
};
struct mlx5_ifc_regexp_params_bits {
u8 reserved_at_0[0x1f];
u8 stop_engine[0x1];
- u8 db_umem_id[0x20];
- u8 db_umem_offset[0x40];
- u8 reserved_at_80[0x100];
+ u8 reserved_at_20[0x60];
+ u8 rof_mkey[0x20];
+ u8 rof_size[0x20];
+ u8 rof_mkey_va[0x40];
+ u8 reserved_at_100[0x80];
};
struct mlx5_ifc_set_regexp_params_in_bits {
MLX5_FLOW_COLOR_UNDEFINED,
};
-/* Maximum value of srTCM metering parameters. */
-#define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
-#define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
-#define MLX5_SRTCM_EBS_MAX 0
+/* Maximum value of srTCM & trTCM metering parameters. */
+#define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F))
+#define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF)
/* The bits meter color use. */
#define MLX5_MTR_COLOR_BITS 8
MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
};
+enum mlx5_parse_graph_flow_match_sample_tunnel_mode {
+ MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0,
+ MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1,
+ MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2
+};
+
/* Node index for an input / output arc of the flex parser graph. */
enum mlx5_parse_graph_arc_node_index {
MLX5_GRAPH_ARC_NODE_NULL = 0x0,
MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
+ MLX5_GRAPH_ARC_NODE_IPV4 = 0xb,
+ MLX5_GRAPH_ARC_NODE_IPV6 = 0xc,
MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
};
+#define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8
+#define MLX5_PARSE_GRAPH_IN_ARC_MAX 8
+#define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8
+
/**
* Convert a user mark to flow mark.
*
git.droids-corp.org / dpdk.git / blobdiff