#ifndef RTE_PMD_MLX5_PRM_H_
#define RTE_PMD_MLX5_PRM_H_
-#include <assert.h>
/* Verbs header. */
/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
#ifdef PEDANTIC
*/
#define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
#define MLX5_MPW_MAX_PACKETS 6
-#define MLX5_MPW_INLINE_MAX_PACKETS 2
+#define MLX5_MPW_INLINE_MAX_PACKETS 6
/*
* Default packet length threshold to be inlined with
/* CQE format value. */
#define MLX5_COMPRESSED 0x3
+/* CQ doorbell cmd types. */
+#define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
+#define MLX5_CQ_DBR_CMD_ALL (0 << 24)
+
/* Action type of header modification. */
enum {
MLX5_MODIFICATION_TYPE_SET = 0x1,
#define MLX5_SET64(typ, p, fld, v) \
do { \
- assert(__mlx5_bit_sz(typ, fld) == 64); \
+ MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
rte_cpu_to_be_64(v); \
} while (0)
u8 tcp_flags[0x9];
u8 tcp_sport[0x10];
u8 tcp_dport[0x10];
- u8 reserved_at_c0[0x20];
+ u8 reserved_at_c0[0x18];
+ u8 ip_ttl_hoplimit[0x8];
u8 udp_sport[0x10];
u8 udp_dport[0x10];
union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
#define MLX5_ADAPTER_PAGE_SHIFT 12
#define MLX5_LOG_RQ_STRIDE_SHIFT 4
+/**
+ * The batch counter dcs id starts from 0x800000 and none batch counter
+ * starts from 0. As currently, the counter is changed to be indexed by
+ * pool index and the offset of the counter in the pool counters_raw array.
+ * It means now the counter index is same for batch and none batch counter.
+ * Add the 0x800000 batch counter offset to the batch counter index helps
+ * indicate the counter index is from batch or none batch container pool.
+ */
+#define MLX5_CNT_BATCH_OFFSET 0x800000
/* Flow counters. */
struct mlx5_ifc_alloc_flow_counter_out_bits {
u8 translations_octword_size[0x20];
- u8 reserved_at_1c0[0x1b];
+ u8 reserved_at_1c0[0x19];
+ u8 relaxed_ordering_read[0x1];
+ u8 reserved_at_1da[0x1];
u8 log_page_size[0x5];
u8 reserved_at_1e0[0x20];