common/mlx5: wrap memory allocation on Linux

[dpdk.git] / drivers / common / mlx5 / mlx5_prm.h

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index ad6dc59..58d1804 100644 (file)
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -120,7 +120,7 @@
                                  MLX5_WQE_DSEG_SIZE + \
                                  MLX5_ESEG_MIN_INLINE_SIZE)
 
-/* Missed in mlv5dv.h, should define here. */
+/* Missed in mlx5dv.h, should define here. */
 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 #endif
@@ -133,6 +133,10 @@
 #define MLX5_OPCODE_WAIT 0x0fu
 #endif
 
+#ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
+#define MLX5_OPCODE_ACCESS_ASO 0x2du
+#endif
+
 /* CQE value to inform that VLAN is stripped. */
 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 
@@ -289,6 +293,15 @@ struct mlx5_wqe_cseg {
        uint32_t misc;
 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 
+/*
+ * WQE CSEG opcode field size is 32 bits, divided:
+ * Bits 31:24 OPC_MOD
+ * Bits 23:8 wqe_index
+ * Bits 7:0 OPCODE
+ */
+#define WQE_CSEG_OPC_MOD_OFFSET                24
+#define WQE_CSEG_WQE_INDEX_OFFSET       8
+
 /* Header of data segment. Minimal size Data Segment */
 struct mlx5_wqe_dseg {
        uint32_t bcount;
@@ -1044,9 +1057,14 @@ enum {
        MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
 };
 
-#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q                 (1ULL << 0xd)
-#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS           (1ULL << 0x1c)
-#define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE       (1ULL << 0x22)
+#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
+                       (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
+#define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
+                       (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
+#define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
+                       (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
+#define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
+                       (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
 
 enum {
        MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
@@ -2350,6 +2368,73 @@ struct mlx5_ifc_create_flow_hit_aso_in_bits {
        struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
 };
 
+enum mlx5_access_aso_opc_mod {
+       ASO_OPC_MOD_IPSEC = 0x0,
+       ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
+       ASO_OPC_MOD_POLICER = 0x2,
+       ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
+       ASO_OPC_MOD_FLOW_HIT = 0x4,
+};
+
+#define ASO_CSEG_DATA_MASK_MODE_OFFSET 30
+
+enum mlx5_aso_data_mask_mode {
+       BITWISE_64BIT = 0x0,
+       BYTEWISE_64BYTE = 0x1,
+       CALCULATED_64BYTE = 0x2,
+};
+
+#define ASO_CSEG_COND_0_OPER_OFFSET    20
+#define ASO_CSEG_COND_1_OPER_OFFSET    16
+
+enum mlx5_aso_pre_cond_op {
+       ASO_OP_ALWAYS_FALSE = 0x0,
+       ASO_OP_ALWAYS_TRUE = 0x1,
+       ASO_OP_EQUAL = 0x2,
+       ASO_OP_NOT_EQUAL = 0x3,
+       ASO_OP_GREATER_OR_EQUAL = 0x4,
+       ASO_OP_LESSER_OR_EQUAL = 0x5,
+       ASO_OP_LESSER = 0x6,
+       ASO_OP_GREATER = 0x7,
+       ASO_OP_CYCLIC_GREATER = 0x8,
+       ASO_OP_CYCLIC_LESSER = 0x9,
+};
+
+#define ASO_CSEG_COND_OPER_OFFSET      6
+
+enum mlx5_aso_op {
+       ASO_OPER_LOGICAL_AND = 0x0,
+       ASO_OPER_LOGICAL_OR = 0x1,
+};
+
+/* ASO WQE CTRL segment. */
+struct mlx5_aso_cseg {
+       uint32_t va_h;
+       uint32_t va_l_r;
+       uint32_t lkey;
+       uint32_t operand_masks;
+       uint32_t condition_0_data;
+       uint32_t condition_0_mask;
+       uint32_t condition_1_data;
+       uint32_t condition_1_mask;
+       uint64_t bitwise_data;
+       uint64_t data_mask;
+} __rte_packed;
+
+#define MLX5_ASO_WQE_DSEG_SIZE 0x40
+
+/* ASO WQE Data segment. */
+struct mlx5_aso_dseg {
+       uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
+} __rte_packed;
+
+/* ASO WQE. */
+struct mlx5_aso_wqe {
+       struct mlx5_wqe_cseg general_cseg;
+       struct mlx5_aso_cseg aso_cseg;
+       struct mlx5_aso_dseg aso_dseg;
+} __rte_packed;
+
 enum {
        MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
 };