raw/octeontx2_ep: add device configuration

[dpdk.git] / drivers / common / octeontx2 / otx2_common.h

diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h
index 58fcf5a..81d5a71 100644 (file)
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -5,14 +5,18 @@
 #ifndef _OTX2_COMMON_H_
 #define _OTX2_COMMON_H_
 
+#include <rte_atomic.h>
 #include <rte_common.h>
-#include <rte_io.h>
+#include <rte_cycles.h>
 #include <rte_memory.h>
+#include <rte_memzone.h>
+#include <rte_io.h>
 
 #include "hw/otx2_rvu.h"
 #include "hw/otx2_nix.h"
 #include "hw/otx2_npc.h"
 #include "hw/otx2_npa.h"
+#include "hw/otx2_sdp.h"
 #include "hw/otx2_sso.h"
 #include "hw/otx2_ssow.h"
 #include "hw/otx2_tim.h"
@@ -28,11 +32,50 @@
 #define BIT(nr)     (1UL << (nr))
 #endif
 
+#ifndef BITS_PER_LONG
+#define BITS_PER_LONG  (__SIZEOF_LONG__ * 8)
+#endif
+#ifndef BITS_PER_LONG_LONG
+#define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
+#endif
+
+#ifndef GENMASK
+#define GENMASK(h, l) \
+               (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+#endif
+#ifndef GENMASK_ULL
+#define GENMASK_ULL(h, l) \
+       (((~0ULL) - (1ULL << (l)) + 1) & \
+        (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
+#endif
+
 /* Compiler attributes */
 #ifndef __hot
 #define __hot   __attribute__((hot))
 #endif
 
+/* Intra device related functions */
+struct otx2_npa_lf;
+struct otx2_idev_cfg {
+       uint16_t sso_pf_func;
+       uint16_t npa_pf_func;
+       struct otx2_npa_lf *npa_lf;
+       RTE_STD_C11
+       union {
+               rte_atomic16_t npa_refcnt;
+               uint16_t npa_refcnt_u16;
+       };
+};
+
+struct otx2_idev_cfg *otx2_intra_dev_get_cfg(void);
+void otx2_sso_pf_func_set(uint16_t sso_pf_func);
+uint16_t otx2_sso_pf_func_get(void);
+uint16_t otx2_npa_pf_func_get(void);
+struct otx2_npa_lf *otx2_npa_lf_obj_get(void);
+void otx2_npa_set_defaults(struct otx2_idev_cfg *idev);
+int otx2_npa_lf_active(void *dev);
+int otx2_npa_lf_obj_ref(void);
+
 /* Log */
 extern int otx2_logtype_base;
 extern int otx2_logtype_mbox;
@@ -43,13 +86,11 @@ extern int otx2_logtype_npc;
 extern int otx2_logtype_tm;
 extern int otx2_logtype_tim;
 extern int otx2_logtype_dpi;
+extern int otx2_logtype_ep;
 
-#define OTX2_CLNRM  "\x1b[0m"
-#define OTX2_CLRED  "\x1b[31m"
-
-#define otx2_err(fmt, args...)                                         \
-       RTE_LOG(ERR, PMD, ""OTX2_CLRED"%s():%u " fmt OTX2_CLNRM"\n",    \
-                               __func__, __LINE__, ## args)
+#define otx2_err(fmt, args...)                 \
+       RTE_LOG(ERR, PMD, "%s():%u " fmt "\n",  \
+               __func__, __LINE__, ## args)
 
 #define otx2_info(fmt, args...)                                                \
        RTE_LOG(INFO, PMD, fmt"\n", ## args)
@@ -68,6 +109,41 @@ extern int otx2_logtype_dpi;
 #define otx2_tm_dbg(fmt, ...) otx2_dbg(tm, fmt, ##__VA_ARGS__)
 #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)
 #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)
+#define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__)
+
+/* PCI IDs */
+#define PCI_VENDOR_ID_CAVIUM                   0x177D
+#define PCI_DEVID_OCTEONTX2_RVU_PF              0xA063
+#define PCI_DEVID_OCTEONTX2_RVU_VF             0xA064
+#define PCI_DEVID_OCTEONTX2_RVU_AF             0xA065
+#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF     0xA0F9
+#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF     0xA0FA
+#define PCI_DEVID_OCTEONTX2_RVU_NPA_PF         0xA0FB
+#define PCI_DEVID_OCTEONTX2_RVU_NPA_VF         0xA0FC
+#define PCI_DEVID_OCTEONTX2_RVU_CPT_PF         0xA0FD
+#define PCI_DEVID_OCTEONTX2_RVU_CPT_VF         0xA0FE
+#define PCI_DEVID_OCTEONTX2_RVU_AF_VF          0xA0f8
+#define PCI_DEVID_OCTEONTX2_DPI_VF             0xA081
+#define PCI_DEVID_OCTEONTX2_EP_VF              0xB203 /* OCTEON TX2 EP mode */
+#define PCI_DEVID_OCTEONTX2_RVU_SDP_PF         0xA0f6
+#define PCI_DEVID_OCTEONTX2_RVU_SDP_VF         0xA0f7
+
+/*
+ * REVID for RVU PCIe devices.
+ * Bits 0..1: minor pass
+ * Bits 3..2: major pass
+ * Bits 7..4: midr id, 0:96, 1:95, 2:loki, f:unknown
+ */
+
+#define RVU_PCI_REV_MIDR_ID(rev_id)            (rev_id >> 4)
+#define RVU_PCI_REV_MAJOR(rev_id)              ((rev_id >> 2) & 0x3)
+#define RVU_PCI_REV_MINOR(rev_id)              (rev_id & 0x3)
+
+#define RVU_PCI_CN96XX_MIDR_ID                 0x0
+#define RVU_PCI_CNF95XX_MIDR_ID                        0x1
+
+/* PCI Config offsets */
+#define RVU_PCI_REVISION_ID                    0x08
 
 /* IO Access */
 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))